{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T05:03:19Z","timestamp":1750309399664,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":10,"publisher":"ACM","license":[{"start":{"date-parts":[[2024,8,5]],"date-time":"2024-08-05T00:00:00Z","timestamp":1722816000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100003725","name":"National Research Foundation of Korea","doi-asserted-by":"publisher","award":["2021R1C1C1008752","2022M3I7A1078936"],"award-info":[{"award-number":["2021R1C1C1008752","2022M3I7A1078936"]}],"id":[{"id":"10.13039\/501100003725","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2024,8,5]]},"DOI":"10.1145\/3665314.3670819","type":"proceedings-article","created":{"date-parts":[[2024,9,9]],"date-time":"2024-09-09T19:31:18Z","timestamp":1725910278000},"page":"1-6","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Coupled 7T 1C SRAM based in-memory computing architecture with gain\/offset error auto-compensated SAR ADC"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0009-0007-1306-2824","authenticated-orcid":false,"given":"Honggu","family":"Kim","sequence":"first","affiliation":[{"name":"Chung-Ang university, Seoul, Dong-jak Gu, Republic of Korea"}]},{"ORCID":"https:\/\/orcid.org\/0009-0008-8939-2368","authenticated-orcid":false,"given":"Yerim","family":"An","sequence":"additional","affiliation":[{"name":"Chung-Ang university, Seoul, Republic of Korea"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7101-6718","authenticated-orcid":false,"given":"Yong","family":"Shim","sequence":"additional","affiliation":[{"name":"Chunag-Ang university, Seoul, Dong-jak Gu, Republic of Korea"}]}],"member":"320","published-online":{"date-parts":[[2024,9,9]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2880918"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC59616.2023.10268706"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"crossref","unstructured":"A. Kneip M. Lefebvre J. Verecken and D. Bol \"A 1-to-4b 16.8-pops\/w 473-tops\/mm2 6t-based in-memory computing sram in 22nm fd-soi with multi-bit analog batch-normalization \" in ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) 2022 pp. 157--160.","DOI":"10.1109\/ESSCIRC55480.2022.9911348"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.2992886"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"crossref","unstructured":"H. Wang R. Liu R. Dorrance D. Dasalukunte X. Liu D. Lake B. Carlton and M. Wu \"A 32.2 tops\/w sram compute-in-memory macro employing a linear 8-bit c-2c ladder for charge domain computation in 22nm for edge inference \" in 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) 2022 pp. 36--37.","DOI":"10.1109\/VLSITechnologyandCir46769.2022.9830322"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/3531437.3539718"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2021.3056447"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"crossref","unstructured":"S.-E. Hsieh C.-H. Wei C.-X. Xue H.-W. Lin W.-H. Tu E.-J. Chang K.-T. Yang P.-H. Chen W.-N. Liao L. L. Low C.-D. Lee A.-C. Lu J. Liang C.-C. Cheng and T.-H. Kang \"7.6 a 70.85-86.27tops\/w pvt-insensitive 8b word-wise acim with post-processing relaxation \" in 2023 IEEE International Solid-State Circuits Conference (ISSCC) 2023 pp. 136--138.","DOI":"10.1109\/ISSCC42615.2023.10067335"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2042254"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/MSSC.2017.2771102"}],"event":{"name":"ISLPED '24: 29th ACM\/IEEE International Symposium on Low Power Electronics and Design","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CAS","IEEE EDA"],"location":"Newport Beach CA USA","acronym":"ISLPED '24"},"container-title":["Proceedings of the 29th ACM\/IEEE International Symposium on Low Power Electronics and Design"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3665314.3670819","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3665314.3670819","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T00:57:51Z","timestamp":1750294671000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3665314.3670819"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,8,5]]},"references-count":10,"alternative-id":["10.1145\/3665314.3670819","10.1145\/3665314"],"URL":"https:\/\/doi.org\/10.1145\/3665314.3670819","relation":{},"subject":[],"published":{"date-parts":[[2024,8,5]]},"assertion":[{"value":"2024-09-09","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}