{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,24]],"date-time":"2025-08-24T00:01:02Z","timestamp":1755993662671,"version":"3.44.0"},"publisher-location":"New York, NY, USA","reference-count":18,"publisher":"ACM","license":[{"start":{"date-parts":[[2024,9,9]],"date-time":"2024-09-09T00:00:00Z","timestamp":1725840000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"DOI":"10.13039\/501100006374","name":"National Science Foundation","doi-asserted-by":"publisher","award":["2322713"],"award-info":[{"award-number":["2322713"]}],"id":[{"id":"10.13039\/501100006374","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2024,9,9]]},"DOI":"10.1145\/3670474.3685939","type":"proceedings-article","created":{"date-parts":[[2024,9,3]],"date-time":"2024-09-03T06:22:27Z","timestamp":1725344547000},"page":"1-7","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Efficient and Effective Neural Networks for Automatic Test Pattern Generation"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0009-0001-3737-4044","authenticated-orcid":false,"given":"Lizi","family":"Zhang","sequence":"first","affiliation":[{"name":"University of Wisconsin-Madison, Madison, Wisconsin, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5213-2556","authenticated-orcid":false,"given":"Azadeh","family":"Davoodi","sequence":"additional","affiliation":[{"name":"University of Wisconsin-Madison, Madison, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2024,9,9]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"On Testability Analysis of Combinational Circuits. IEEE International Symposium on Circuits and Systems","author":"Brglez F.","year":"1984","unstructured":"F. Brglez. 1984. On Testability Analysis of Combinational Circuits. IEEE International Symposium on Circuits and Systems (1984), 221--225."},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"crossref","first-page":"1137","DOI":"10.1109\/TC.1983.1676174","article-title":"On the Acceleration of Test Generation Algorithms","volume":"12","author":"Shimono Fujiwara","year":"1983","unstructured":"Fujiwara and Shimono. 1983. On the Acceleration of Test Generation Algorithms. IEEE Trans. Comput. C-32, 12 (1983), 1137--1144.","journal-title":"IEEE Trans. Comput. C-32"},{"key":"e_1_3_2_1_3_1","unstructured":"H. K. Lee and D. S. Ha. 1993. On the Generation of Test Patterns for Combinational Circuits. Technical Report No. 12--93. Department of Electrical Engineering Virginia Polytechnic Institute and State University."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/PGEC.1967.264743"},{"key":"e_1_3_2_1_5_1","volume-title":"First International Workshop on VLSI Design","author":"Patel J.","year":"1985","unstructured":"J. Patel and S. Patel. 1985. What Heuristics are Best for PODEM? First International Workshop on VLSI Design (1985), 1--20."},{"key":"e_1_3_2_1_6_1","volume-title":"On Removing Redundancy in Sequential Circuits. ACM\/IEEE Design Automation Conference","author":"Cheng K. T.","year":"1991","unstructured":"K. T. Cheng. 1991. On Removing Redundancy in Sequential Circuits. ACM\/IEEE Design Automation Conference (1991), 164--169."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCS.1979.1084687"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1023\/A:1008207423859"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.31539"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1975.224205"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1981.1675757"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1049\/ip-e.1981.0037"},{"key":"e_1_3_2_1_13_1","volume-title":"Effectiveness of Heuristics Measures for Automatic Test Pattern Generation. ACM\/IEEE Design Automation Conference","author":"Patel S.","year":"1986","unstructured":"S. Patel and J. Patel. 1986. Effectiveness of Heuristics Measures for Automatic Test Pattern Generation. ACM\/IEEE Design Automation Conference (1986), 547--552."},{"key":"e_1_3_2_1_14_1","volume-title":"Machine Intelligence for Efficient Test Pattern Generation. IEEE International Test Conference","author":"Roy S.","year":"2020","unstructured":"S. Roy, S. K. Millican, and V. D. Agrawal. 2020. Machine Intelligence for Efficient Test Pattern Generation. IEEE International Test Conference (2020), 1--5."},{"key":"e_1_3_2_1_15_1","volume-title":"Training Neural Network for Machine Intelligence in Automatic Test Pattern Generator. IEEE International Conference on VLSI Design and International Conference on Embedded Systems","author":"Roy S.","year":"2021","unstructured":"S. Roy, S. K. Millican, and V. D. Agrawal. 2021. Training Neural Network for Machine Intelligence in Automatic Test Pattern Generator. IEEE International Conference on VLSI Design and International Conference on Embedded Systems (2021), 316--321."},{"key":"e_1_3_2_1_16_1","volume-title":"Unsupervised Learning in Test Generation for Digital Integrated Circuits. IEEE European Test Symposium","author":"Roy S.","year":"2021","unstructured":"S. Roy, S. K. Millican, and V. D. Agrawal. 2021. Unsupervised Learning in Test Generation for Digital Integrated Circuits. IEEE European Test Symposium (2021), 1--4."},{"key":"e_1_3_2_1_17_1","volume-title":"Multi-Heuristic Machine Intelligence Guidance in Automatic Test Pattern Generation. IEEE Microelectronics Design & Test Symposium","author":"Roy S.","year":"2022","unstructured":"S. Roy, S. K. Millican, and V. D. Agrawal. 2022. Multi-Heuristic Machine Intelligence Guidance in Automatic Test Pattern Generation. IEEE Microelectronics Design & Test Symposium (2022), 1--6."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"crossref","unstructured":"S. T. Chakradhar V. D. Agrawal and M. L. Bushnell. 1991. Neural Models and Algorithms for Digital Testing. Springer.","DOI":"10.1007\/978-1-4615-3958-2"}],"event":{"name":"MLCAD '24: 2024 ACM\/IEEE International Symposium on Machine Learning for CAD","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CEDA"],"location":"Salt Lake City UT USA","acronym":"MLCAD '24"},"container-title":["Proceedings of the 2024 ACM\/IEEE International Symposium on Machine Learning for CAD"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3670474.3685939","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3670474.3685939","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,22]],"date-time":"2025-08-22T23:43:19Z","timestamp":1755906199000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3670474.3685939"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,9,9]]},"references-count":18,"alternative-id":["10.1145\/3670474.3685939","10.1145\/3670474"],"URL":"https:\/\/doi.org\/10.1145\/3670474.3685939","relation":{},"subject":[],"published":{"date-parts":[[2024,9,9]]},"assertion":[{"value":"2024-09-09","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}