{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T05:06:49Z","timestamp":1750309609951,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":8,"publisher":"ACM","license":[{"start":{"date-parts":[[2025,3,31]],"date-time":"2025-03-31T00:00:00Z","timestamp":1743379200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100018699","name":"HORIZON EUROPE Digital, Industry and Space","doi-asserted-by":"publisher","award":["101070238"],"award-info":[{"award-number":["101070238"]}],"id":[{"id":"10.13039\/100018699","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Departament de Recerca i Universitats de la Generalitat de Catalunya","award":["2021 SGR 00637"],"award-info":[{"award-number":["2021 SGR 00637"]}]},{"DOI":"10.13039\/501100000038","name":"Natural Sciences and Engineering Research Council of Canada","doi-asserted-by":"publisher","award":["RGPIN-2019-05727"],"award-info":[{"award-number":["RGPIN-2019-05727"]}],"id":[{"id":"10.13039\/501100000038","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2025,3,31]]},"DOI":"10.1145\/3672608.3707822","type":"proceedings-article","created":{"date-parts":[[2025,5,14]],"date-time":"2025-05-14T18:30:17Z","timestamp":1747247417000},"page":"588-589","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["On the Time Predictability of AXI4"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-1960-6358","authenticated-orcid":false,"given":"Roger","family":"Pujol","sequence":"first","affiliation":[{"name":"Barcelona Supercomputing Center, Barcelona, Spain"},{"name":"Universitat Polit\u00e8cnica de Catalunya, Barcelona, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7951-4028","authenticated-orcid":false,"given":"Jaume","family":"Abella","sequence":"additional","affiliation":[{"name":"Barcelona Supercomputing Center, Barcelona, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5926-5861","authenticated-orcid":false,"given":"Mohamed","family":"Hassan","sequence":"additional","affiliation":[{"name":"McMaster University, Hamilton, Canada"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3344-376X","authenticated-orcid":false,"given":"Francisco Javier","family":"Cazorla","sequence":"additional","affiliation":[{"name":"Barcelona Supercomputing Center, Barcelona, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2025,5,14]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"Arm. 2013. AMBA AXI and ACE Protocol Specification AXI3 AXI4 and AXI4-Lite ACE and ACE-Lite. ARM IHI 0022E (ID033013)."},{"key":"e_1_3_2_1_2_1","unstructured":"Arm. 2022. AMBA 5 CHI Architecture Specification. ARM IHI 0050F (ID092622))."},{"key":"e_1_3_2_1_3_1","volume-title":"35th Euromicro Conference on Real-Time Systems, ECRTS 2023","volume":"25","author":"Garcia-Esteban Sergio","year":"2023","unstructured":"Sergio Garcia-Esteban, Alejandro Serrano-Cases, Jaume Abella, Enrico Mezzetti, and Francisco J. Cazorla. 2023. Quasi Isolation QoS Setups to Control MPSoC Contention in Integrated Software Architectures. In 35th Euromicro Conference on Real-Time Systems, ECRTS 2023, July 11\u201314, 2023, Vienna, Austria (LIPIcs, Vol. 262). 5:1\u20135:25."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18072.2020.9218652"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/3358183"},{"key":"e_1_3_2_1_6_1","volume-title":"33rd Euromicro Conference on Real-Time Systems, ECRTS 2021, July 5\u20139, 2021, Virtual Conference (LIPIcs","volume":"26","author":"Serrano-Cases Alejandro","unstructured":"Alejandro Serrano-Cases, Juan M. Reina, Jaume Abella, Enrico Mezzetti, and Francisco J. Cazorla. 2021. Leveraging Hardware QoS to Control Contention in the Xilinx Zynq UltraScale+ MPSoC. In 33rd Euromicro Conference on Real-Time Systems, ECRTS 2021, July 5\u20139, 2021, Virtual Conference (LIPIcs, Vol. 196). 3:1\u20133:26."},{"key":"e_1_3_2_1_7_1","unstructured":"SiFive. 2017. SiFive TileLink Specification."},{"key":"e_1_3_2_1_8_1","unstructured":"XILINX. 2019. Zynq UltraScale+ Device. Technical Reference Manual. UG1085 (v2.1). https:\/\/docs.xilinx.com\/r\/en-US\/ug1085-zynq-ultrascale-trm"}],"event":{"name":"SAC '25: 40th ACM\/SIGAPP Symposium on Applied Computing","sponsor":["SIGAPP ACM Special Interest Group on Applied Computing"],"location":"Catania International Airport Catania Italy","acronym":"SAC '25"},"container-title":["Proceedings of the 40th ACM\/SIGAPP Symposium on Applied Computing"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3672608.3707822","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3672608.3707822","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T01:57:33Z","timestamp":1750298253000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3672608.3707822"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,3,31]]},"references-count":8,"alternative-id":["10.1145\/3672608.3707822","10.1145\/3672608"],"URL":"https:\/\/doi.org\/10.1145\/3672608.3707822","relation":{},"subject":[],"published":{"date-parts":[[2025,3,31]]},"assertion":[{"value":"2025-05-14","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}