{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,1]],"date-time":"2026-02-01T03:00:52Z","timestamp":1769914852005,"version":"3.49.0"},"reference-count":22,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2024,9,30]],"date-time":"2024-09-30T00:00:00Z","timestamp":1727654400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Reconfigurable Technol. Syst."],"published-print":{"date-parts":[[2024,9,30]]},"abstract":"<jats:p>\n            This manuscript makes the claim of having computed the\n            <jats:inline-formula content-type=\"math\/tex\">\n              <jats:tex-math notation=\"LaTeX\" version=\"MathJax\">\\(9\\)<\/jats:tex-math>\n            <\/jats:inline-formula>\n            th Dedekind number, D(9). This was done by accelerating the core operation of the process with an efficient FPGA design that outperforms an optimized 64-core CPU reference by 95\n            <jats:inline-formula content-type=\"math\/tex\">\n              <jats:tex-math notation=\"LaTeX\" version=\"MathJax\">\\(\\times\\)<\/jats:tex-math>\n            <\/jats:inline-formula>\n            . The FPGA execution was parallelized on the Noctua 2 supercomputer at Paderborn University. The resulting value for D(9) is 286386577668298411128469151667598498812366. This value can be verified in two steps. We have made the data file containing the 490 M results available, each of which can be verified separately on CPU, and the whole file sums to our proposed value. The paper explains the mathematical approach in the first part, before putting the focus on a deep dive into the FPGA accelerator implementation followed by a performance analysis. The FPGA implementation was done in Register-Transfer Level using a dual-clock architecture and shows how we achieved an impressive FMax of 450 MHz on the targeted Stratix 10 GX 2,800 FPGAs. The total compute time used was 47,000 FPGA hours.\n          <\/jats:p>","DOI":"10.1145\/3674147","type":"journal-article","created":{"date-parts":[[2024,7,2]],"date-time":"2024-07-02T20:44:52Z","timestamp":1719953092000},"page":"1-28","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["A Computation of the Ninth Dedekind Number Using FPGA Supercomputing"],"prefix":"10.1145","volume":"17","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-6982-8012","authenticated-orcid":false,"given":"Lennart","family":"Van Hirtum","sequence":"first","affiliation":[{"name":"Paderborn Center for Parallel Computing, Paderborn University, Paderborn, Germany"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6763-1945","authenticated-orcid":false,"given":"Patrick","family":"De Causmaecker","sequence":"additional","affiliation":[{"name":"KU Leuven, Department of Computer Science, CODeS research group, Kortrijk, Belgium"}]},{"ORCID":"https:\/\/orcid.org\/0009-0003-9763-7680","authenticated-orcid":false,"given":"Jens","family":"Goemaere","sequence":"additional","affiliation":[{"name":"KU Leuven, Department of Computer Science, CODeS research group, Kortrijk, Belgium"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5088-0267","authenticated-orcid":false,"given":"Tobias","family":"Kenter","sequence":"additional","affiliation":[{"name":"Paderborn Center for Parallel Computing, Paderborn University, Paderborn, Germany"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3811-894X","authenticated-orcid":false,"given":"Heinrich","family":"Riebler","sequence":"additional","affiliation":[{"name":"Paderborn Center for Parallel Computing, Paderborn University, Paderborn, Germany"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5708-7632","authenticated-orcid":false,"given":"Michael","family":"Lass","sequence":"additional","affiliation":[{"name":"Paderborn Center for Parallel Computing, Paderborn University, Paderborn, Germany"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5728-9982","authenticated-orcid":false,"given":"Christian","family":"Plessl","sequence":"additional","affiliation":[{"name":"Paderborn Center for Parallel Computing, Paderborn University, Paderborn, Germany"}]}],"member":"320","published-online":{"date-parts":[[2024,9,30]]},"reference":[{"key":"e_1_3_2_2_2","doi-asserted-by":"publisher","DOI":"10.17815\/jlsrf-8-187"},{"key":"e_1_3_2_3_2","doi-asserted-by":"publisher","DOI":"10.48550\/arXiv.2405.20904"},{"key":"e_1_3_2_4_2","doi-asserted-by":"publisher","DOI":"10.48550\/arXiv.1103.2877"},{"key":"e_1_3_2_5_2","doi-asserted-by":"publisher","DOI":"10.48550\/arXiv.1407.4288"},{"key":"e_1_3_2_6_2","doi-asserted-by":"publisher","DOI":"10.48550\/arXiv.1602.04675"},{"key":"e_1_3_2_7_2","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-663-07224-9_1"},{"key":"e_1_3_2_8_2","doi-asserted-by":"publisher","DOI":"10.1109\/CCECE.2001.933564"},{"key":"e_1_3_2_9_2","volume-title":"A Path to Compute the 9th Dedekind Number using FPGA Supercomputing","author":"Hirtum Lennart Van","year":"2021","unstructured":"Lennart Van Hirtum. 2021. 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