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Syst."],"published-print":{"date-parts":[[2024,9,30]]},"abstract":"<jats:p>\n            FPGAs have been shown to operate reliably within harsh radiation environments by employing single-event upset (SEU) mitigation techniques, such as configuration scrubbing, triple-modular redundancy, error correction coding, and radiation aware implementation techniques. The effectiveness of these techniques, however, is limited when using complex system-level designs that employ complex I\/O interfaces with single-point failures. In previous work, a complex SoC system running Linux applied several of these techniques only to obtain an improvement of 14\n            <jats:inline-formula content-type=\"math\/tex\">\n              <jats:tex-math notation=\"LaTeX\" version=\"MathJax\">\\(\\times\\)<\/jats:tex-math>\n            <\/jats:inline-formula>\n            in mean time to failure (MTTF). A detailed post-radiation fault analysis found that the limitations in reliability were due to the DDR interface, the global clock network, and interconnect. This article applied a number of design-specific SEU mitigation techniques to address the limitations in reliability of this design. These changes include triplicating the global clock, optimizing the placement of the reduction output voters and input flip-flops, and employing a mapping technique called \u201cstriping.\u201d The application of these techniques improved MTTF of the mitigated design by a factor of 1.54\n            <jats:inline-formula content-type=\"math\/tex\">\n              <jats:tex-math notation=\"LaTeX\" version=\"MathJax\">\\(\\times\\)<\/jats:tex-math>\n            <\/jats:inline-formula>\n            and thus provides a 22.8X\n            <jats:inline-formula content-type=\"math\/tex\">\n              <jats:tex-math notation=\"LaTeX\" version=\"MathJax\">\\(\\times\\)<\/jats:tex-math>\n            <\/jats:inline-formula>\n            MTTF improvement over the unmitigated design. A post-radiation fault analysis using BFAT was also performed to find the remaining design vulnerabilities.\n          <\/jats:p>","DOI":"10.1145\/3674841","type":"journal-article","created":{"date-parts":[[2024,7,19]],"date-time":"2024-07-19T17:28:05Z","timestamp":1721410085000},"page":"1-21","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["Improving Fault Tolerance for FPGA SoCs through Post-Radiation Design Analysis"],"prefix":"10.1145","volume":"17","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-3421-5766","authenticated-orcid":false,"given":"Andrew Elbert","family":"Wilson","sequence":"first","affiliation":[{"name":"Brigham Young University, Provo, Utah, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8364-2970","authenticated-orcid":false,"given":"Nathan","family":"Baker","sequence":"additional","affiliation":[{"name":"Brigham Young University, Provo, Utah, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5208-1805","authenticated-orcid":false,"given":"Ethan","family":"Campbell","sequence":"additional","affiliation":[{"name":"Brigham Young University, Provo, Utah, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0328-6713","authenticated-orcid":false,"given":"Michael","family":"Wirthlin","sequence":"additional","affiliation":[{"name":"Brigham Young University, Provo, Utah, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2024,9,30]]},"reference":[{"key":"e_1_3_1_2_2","volume-title":"Measurement and Reporting of Alpha Particles and Terrestrial Cosmic Ray-Induced Soft Errors in Semiconductor Devices","year":"2001","unstructured":"2001. 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