{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,21]],"date-time":"2026-03-21T19:15:20Z","timestamp":1774120520613,"version":"3.50.1"},"reference-count":43,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2024,11,19]],"date-time":"2024-11-19T00:00:00Z","timestamp":1731974400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Archit. Code Optim."],"published-print":{"date-parts":[[2024,12,31]]},"abstract":"<jats:p>Hardware prefetching plays an important role in modern processors for hiding memory access latency. Delta prefetchers show great potential at the L1D cache level, as they can impose small storage overhead by recording deltas. Furthermore, local delta prefetchers, such as Berti, have been shown to achieve high L1D accuracy. However, there is still room for improving the L1D coverage of existing delta prefetchers. Our goal is to develop a delta prefetcher capable of achieving both high L1D coverage and accuracy. We explore delta prefetchers trained on various types of contextual information, ranging from coarse-grained to fine-grained, and analyze their L1D coverage and accuracy. Our findings indicate that training deltas based on the access histories of both PCs and memory pages for individual PCs and memory pages can lead to increased L1D coverage alongside high accuracy. Therefore, we introduce Hyperion, a highly efficient Page and PC-based delta prefetcher. In terms of the vital component of recording access histories, we implement three different structures and engage in a detailed discussion about them. Furthermore, Hyperion utilizes micro-architecture information (e.g., L1D hits or misses, PQ occupancy) and real-time L1D accuracy to dynamically adjust its issuing mechanism, further enhancing performance and L1D accuracy. Our results show that Hyperion achieves an L1D accuracy of 92.4% and an L1D coverage of 51.9%, along with an L2C coverage of 63.0% and an LLC coverage of 67.5% across a diverse range of applications, including SPEC CPU2006, SPEC CPU2017, GAP, and PARSEC, with a baseline of no prefetching. Regarding performance, Hyperion achieves a 50.1% performance gain, outperforming the state-of-the-art delta prefetcher Berti by 5.0% over baseline across all memory-intensive traces from the four benchmark suites.<\/jats:p>","DOI":"10.1145\/3675398","type":"journal-article","created":{"date-parts":[[2024,7,1]],"date-time":"2024-07-01T11:12:34Z","timestamp":1719832354000},"page":"1-27","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["Hyperion: A Highly Effective Page and PC Based Delta Prefetcher"],"prefix":"10.1145","volume":"21","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-9289-1845","authenticated-orcid":false,"given":"Yujie","family":"Cui","sequence":"first","affiliation":[{"name":"School of Computer Science, Engineering Research Center of Microprocessor &amp; System, Peking University, Beijing, China"}]},{"ORCID":"https:\/\/orcid.org\/0009-0005-9804-5614","authenticated-orcid":false,"given":"Wei","family":"Chen","sequence":"additional","affiliation":[{"name":"School of Computer Science, Engineering Research Center of Microprocessor &amp; System, Peking University, Beijing, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5544-8852","authenticated-orcid":false,"given":"Xu","family":"Cheng","sequence":"additional","affiliation":[{"name":"School of Computer Science, Engineering Research Center of Microprocessor &amp; System, Peking University, Beijing, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4401-3551","authenticated-orcid":false,"given":"Jiangfang","family":"Yi","sequence":"additional","affiliation":[{"name":"School of Computer Science, Engineering Research Center of Microprocessor &amp; System, Peking University, Beijing, China"}]}],"member":"320","published-online":{"date-parts":[[2024,11,19]]},"reference":[{"key":"e_1_3_2_2_2","doi-asserted-by":"publisher","DOI":"10.1145\/2086696.2086698"},{"key":"e_1_3_2_3_2","doi-asserted-by":"publisher","DOI":"10.1145\/125826.125932"},{"key":"e_1_3_2_4_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2018.00021"},{"key":"e_1_3_2_5_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2019.00053"},{"key":"e_1_3_2_6_2","article-title":"The GAP benchmark suite","volume":"1508","author":"Beamer Scott","year":"2015","unstructured":"Scott Beamer, Krste Asanovic, and David A. Patterson. 2015. The GAP benchmark suite. CoRR abs\/1508.03619 (2015).","journal-title":"CoRR"},{"key":"e_1_3_2_7_2","doi-asserted-by":"publisher","DOI":"10.1145\/3466752.3480114"},{"key":"e_1_3_2_8_2","doi-asserted-by":"publisher","DOI":"10.1145\/3352460.3358325"},{"key":"e_1_3_2_9_2","doi-asserted-by":"publisher","DOI":"10.1145\/3307650.3322207"},{"key":"e_1_3_2_10_2","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454128"},{"key":"e_1_3_2_11_2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.39"},{"key":"e_1_3_2_12_2","volume-title":"ChampSim: An Open-source Trace based Simulator","author":"Contributors ChampSim","year":"2023","unstructured":"ChampSim Contributors. 2023. ChampSim: An Open-source Trace based Simulator. Retrieved from https:\/\/github.com\/ChampSim\/ChampSim"},{"key":"e_1_3_2_13_2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2023.3254918"},{"key":"e_1_3_2_14_2","first-page":"82","volume-title":"Proceedings of the IEEE International Symposium on High-Performance Computer Architecture (HPCA\u201922)","author":"Cui Yujie","year":"2022","unstructured":"Yujie Cui, Chun Yang, and Xu Cheng. 2022. Abusing cache line dirty states to leak information in commercial processors. In Proceedings of the IEEE International Symposium on High-Performance Computer Architecture (HPCA\u201922). IEEE, 82\u201397."},{"key":"e_1_3_2_15_2","volume-title":"The 2nd Data Prefetching Championship (DPC2)","author":"DPC2","year":"2015","unstructured":"DPC2. 2015. The 2nd Data Prefetching Championship (DPC2). Retrieved from https:\/\/comparch-conf.gatech.edu\/dpc2\/"},{"key":"e_1_3_2_16_2","volume-title":"The 3rd Data Prefetching Championship (DPC3)","author":"DPC3","year":"2019","unstructured":"DPC3. 2019. The 3rd Data Prefetching Championship (DPC3). Retrieved from https:\/\/dpc3.compas.cs.stonybrook.edu\/"},{"key":"e_1_3_2_17_2","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669154"},{"key":"e_1_3_2_18_2","first-page":"105","volume-title":"Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software","author":"Ferdman Michael","year":"2007","unstructured":"Michael Ferdman and Babak Falsafi. 2007. Last-touch correlated data streaming. In Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software. IEEE Computer Society, 105\u2013115."},{"key":"e_1_3_2_19_2","series-title":"Proceedings of Machine Learning Research","first-page":"1924","volume-title":"Proceedings of the 35th International Conference on Machine Learning (ICML\u201918)","volume":"80","author":"Hashemi Milad","year":"2018","unstructured":"Milad Hashemi, Kevin Swersky, Jamie A. Smith, Grant Ayers, Heiner Litz, Jichuan Chang, Christos Kozyrakis, and Parthasarathy Ranganathan. 2018. Learning memory access patterns. In Proceedings of the 35th International Conference on Machine Learning (ICML\u201918)(Proceedings of Machine Learning Research, Vol. 80), Jennifer G. Dy and Andreas Krause (Eds.). PMLR, 1924\u20131933."},{"key":"e_1_3_2_20_2","first-page":"317","volume-title":"Proceedings of the 9th International Symposium on High-Performance Computer Architecture (HPCA\u201903)","author":"Hu Zhigang","year":"2003","unstructured":"Zhigang Hu, Margaret Martonosi, and Stefanos Kaxiras. 2003. TCP: Tag correlating prefetchers. In Proceedings of the 9th International Symposium on High-Performance Computer Architecture (HPCA\u201903). IEEE Computer Society, 317\u2013326."},{"key":"e_1_3_2_21_2","doi-asserted-by":"publisher","DOI":"10.1145\/1006209.1006211"},{"key":"e_1_3_2_22_2","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540730"},{"key":"e_1_3_2_23_2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO56248.2022.00071"},{"key":"e_1_3_2_24_2","doi-asserted-by":"crossref","first-page":"252","DOI":"10.1145\/264107.264207","volume-title":"Proceedings of the 24th International Symposium on Computer Architecture (ISCA\u201997)","author":"Joseph Doug","year":"1997","unstructured":"Doug Joseph and Dirk Grunwald. 1997. Prefetching using Markov predictors. In Proceedings of the 24th International Symposium on Computer Architecture (ISCA\u201997), Andrew R. Pleszkun and Trevor N. Mudge (Eds.). ACM, 252\u2013263."},{"key":"e_1_3_2_25_2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2016.7783763"},{"key":"e_1_3_2_26_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2016.7446087"},{"key":"e_1_3_2_27_2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO56248.2022.00072"},{"key":"e_1_3_2_28_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA45697.2020.00021"},{"key":"e_1_3_2_29_2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2016.2547392"},{"key":"e_1_3_2_30_2","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2015.2428703"},{"key":"e_1_3_2_31_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835971"},{"key":"e_1_3_2_32_2","article-title":"Berti: A per-page best-request-time delta prefetcher","author":"Ros Alberto","year":"2019","unstructured":"Alberto Ros. 2019. Berti: A per-page best-request-time delta prefetcher. The 3rd Data Prefetching Championship (2019). https:\/\/api.semanticscholar.org\/CorpusID:208008184","journal-title":"The 3rd Data Prefetching Championship"},{"key":"e_1_3_2_33_2","article-title":"Multi-lookahead offset prefetching","author":"Shakerinava Mehran","year":"2019","unstructured":"Mehran Shakerinava, Mohammad Bakhshalipour, Pejman Lotfi-Kamran, and Hamid Sarbazi-Azad. 2019. Multi-lookahead offset prefetching. The Third Data Prefetching Championship (2019). https:\/\/api.semanticscholar.org\/CorpusID:199570386","journal-title":"The Third Data Prefetching Championship"},{"key":"e_1_3_2_34_2","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830793"},{"key":"e_1_3_2_35_2","doi-asserted-by":"publisher","DOI":"10.1145\/3445814.3446752"},{"key":"e_1_3_2_36_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2002.1003576"},{"key":"e_1_3_2_37_2","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555766"},{"key":"e_1_3_2_38_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2006.38"},{"key":"e_1_3_2_39_2","volume-title":"SPEC CPU 2006 Benchmark Suite","author":"SPEC CPU","year":"2006","unstructured":"SPEC CPU. 2006. SPEC CPU 2006 Benchmark Suite. Retrieved from https:\/\/www.spec.org\/cpu2006\/"},{"key":"e_1_3_2_40_2","volume-title":"SPEC CPU 2017 Benchmark Package","author":"SPEC CPU","year":"2017","unstructured":"SPEC CPU. 2017. SPEC CPU 2017 Benchmark Package. Retrieved from https:\/\/www.spec.org\/cpu2017\/"},{"key":"e_1_3_2_41_2","first-page":"73","volume-title":"Proceedings of the IEEE International Conference on Computer Design (ICCD\u201917)","author":"Varkey Dennis Antony","year":"2017","unstructured":"Dennis Antony Varkey, Biswabandan Panda, and Madhu Mutyam. 2017. RCTP: Region correlated temporal prefetcher. In Proceedings of the IEEE International Conference on Computer Design (ICCD\u201917). IEEE Computer Society, 73\u201380."},{"key":"e_1_3_2_42_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.50"},{"key":"e_1_3_2_43_2","doi-asserted-by":"publisher","DOI":"10.1145\/3352460.3358300"},{"key":"e_1_3_2_44_2","doi-asserted-by":"publisher","DOI":"10.1145\/3307650.3322225"}],"container-title":["ACM Transactions on Architecture and Code Optimization"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3675398","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3675398","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T00:04:23Z","timestamp":1750291463000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3675398"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,11,19]]},"references-count":43,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2024,12,31]]}},"alternative-id":["10.1145\/3675398"],"URL":"https:\/\/doi.org\/10.1145\/3675398","relation":{},"ISSN":["1544-3566","1544-3973"],"issn-type":[{"value":"1544-3566","type":"print"},{"value":"1544-3973","type":"electronic"}],"subject":[],"published":{"date-parts":[[2024,11,19]]},"assertion":[{"value":"2024-02-05","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2024-06-19","order":2,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2024-11-19","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}