{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,6]],"date-time":"2026-03-06T19:00:35Z","timestamp":1772823635639,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":54,"publisher":"ACM","license":[{"start":{"date-parts":[[2024,10,27]],"date-time":"2024-10-27T00:00:00Z","timestamp":1729987200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2024,10,27]]},"DOI":"10.1145\/3676536.3676648","type":"proceedings-article","created":{"date-parts":[[2025,4,9]],"date-time":"2025-04-09T13:26:26Z","timestamp":1744205186000},"page":"1-9","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":8,"title":["ATPlace2.5D: Analytical Thermal-Aware Chiplet Placement Framework for Large-Scale 2.5D-IC"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-5155-1553","authenticated-orcid":false,"given":"Qipan","family":"Wang","sequence":"first","affiliation":[{"name":"Academy for Advanced Interdisciplinary Studies; School of Integrated Circuits, Peking University, Beijing, China"}]},{"ORCID":"https:\/\/orcid.org\/0009-0008-9465-4764","authenticated-orcid":false,"given":"Xueqing","family":"Li","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Peking University, Beijing, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4570-4613","authenticated-orcid":false,"given":"Tianyu","family":"Jia","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Peking University, Beijing, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0977-2774","authenticated-orcid":false,"given":"Yibo","family":"Lin","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Peking University, Beijing, China"},{"name":"Institute of Electronic Design Automation, Peking University, Wuxi, JiangSu, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7514-0767","authenticated-orcid":false,"given":"Runsheng","family":"Wang","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Peking University, Beijing, China"},{"name":"Institute of Electronic Design Automation, Peking University, Wuxi, JiangSu, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8146-4821","authenticated-orcid":false,"given":"Ru","family":"Huang","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Peking University, Beijing, China"},{"name":"Institute of Electronic Design Automation, Peking University, Wuxi, JiangSu, China"}]}],"member":"320","published-online":{"date-parts":[[2025,4,9]]},"reference":[{"key":"e_1_3_2_1_1_1","first-page":"57","volume-title":"IEEE","author":"Naffziger S.","year":"2021","unstructured":"S. Naffziger, N. Beck, T. Burd, K. Lepak, G. H. Loh, M. Subramony, and S. White, \"Pioneering chiplet technology and design for the amd epyc\u2122 and ryzen\u2122 processor families: Industrial product,\" in 2021 ACM\/IEEE 48th Annual International Symposium on Computer Architecture (ISCA). IEEE, 2021, pp. 57--70."},{"key":"e_1_3_2_1_2_1","first-page":"1","volume-title":"Automation & Test in Europe Conference & Exhibition (DATE). IEEE","author":"Loh G. H.","year":"2023","unstructured":"G. H. Loh and R. Swaminathan, \"The next era for chiplet innovation,\" in 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2023, pp. 1--6."},{"key":"e_1_3_2_1_3_1","first-page":"1","volume-title":"Automated design of chiplets,\" in Proceedings of the 2023 International Symposium on Physical Design","author":"Sangiovanni-Vincentelli A.","year":"2023","unstructured":"A. Sangiovanni-Vincentelli, Z. Liang, Z. Zhou, and J. Zhang, \"Automated design of chiplets,\" in Proceedings of the 2023 International Symposium on Physical Design, 2023, pp. 1--8."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"crossref","unstructured":"Y.-K. Ho and Y.-W. Chang \"Multiple chip planning for chip-interposer codesign \" in Proceedings of the 50th Annual Design Automation Conference 2013 pp. 1--6.","DOI":"10.1145\/2463209.2488767"},{"key":"e_1_3_2_1_5_1","first-page":"524","volume-title":"IEEE","author":"Seemuth D. P.","year":"2015","unstructured":"D. P. Seemuth, A. Davoodi, and K. Morrow, \"Automatic die placement and flexible i\/o assignment in 2.5 d ic design,\" in Sixteenth International Symposium on Quality Electronic Design. IEEE, 2015, pp. 524--527."},{"key":"e_1_3_2_1_6_1","first-page":"1246","volume-title":"Automation & Test in Europe Conference & Exhibition (DATE). IEEE","author":"Ma Y.","year":"2021","unstructured":"Y. Ma, L. Delshadtehrani, C. Demirkiran, J. L. Abellan, and A. Joshi, \"Tap-2.5 d: A thermally-aware chiplet placement methodology for 2.5 d systems,\" in 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2021, pp. 1246--1251."},{"key":"e_1_3_2_1_7_1","first-page":"513","volume-title":"IEEE","author":"Osmolovskyi S.","year":"2018","unstructured":"S. Osmolovskyi, J. Knechtel, I. L. Markov, and J. Lienig, \"Optimal die placement for interposer-based 3d ics,\" in 2018 23rd Asia and South Pacific design automation conference (ASP-DAC). IEEE, 2018, pp. 513--520."},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"crossref","unstructured":"H.-W. Chiou J.-H. Jiang Y.-T. Chang Y.-M. Lee and C.-W. Pan \"Chiplet placement for 2.5 d ic with sequence pair based tree and thermal consideration \" in Proceedings of the 28th Asia and South Pacific Design Automation Conference 2023 pp. 7--12.","DOI":"10.1145\/3566097.3567911"},{"key":"e_1_3_2_1_9_1","volume-title":"Rlplanner: Reinforcement learning based floorplanning for chiplets with fast thermal analysis","author":"Duan Y.","year":"2024","unstructured":"Y. Duan, X. Liu, Z. Yu, H. Wu, L. Shao, and X. Zhu, \"Rlplanner: Reinforcement learning based floorplanning for chiplets with fast thermal analysis,\" 2024."},{"key":"e_1_3_2_1_10_1","volume-title":"Chiplet placement order exploration based on learning to rank with graph representation,\" arXiv preprint arXiv:2404.04943","author":"Deng Z.","year":"2024","unstructured":"Z. Deng, Y. Duan, L. Shao, and X. Zhu, \"Chiplet placement order exploration based on learning to rank with graph representation,\" arXiv preprint arXiv:2404.04943, 2024."},{"key":"e_1_3_2_1_11_1","first-page":"000","volume-title":"International Microelectronics Assembly and Packaging Society","author":"Nasrullah J.","year":"2019","unstructured":"J. Nasrullah, Z. Luo, and G. Taylor, \"Designing software configurable chips and sips using chiplets and zglue,\" in International Symposium on Microelectronics, vol. 2019, no. 1. International Microelectronics Assembly and Packaging Society, 2019, pp. 000 027--000 032."},{"key":"e_1_3_2_1_12_1","first-page":"395","volume-title":"IEEE","author":"Ehrett P.","year":"2021","unstructured":"P. Ehrett, T. Austin, and V. Bertacco, \"Chopin: Composing cost-effective custom chips with algorithmic chiplets,\" in 2021 IEEE 39th International Conference on Computer Design (ICCD). IEEE, 2021, pp. 395--399."},{"key":"e_1_3_2_1_13_1","first-page":"1","volume-title":"ITG\/GMM\/GI-Symposium. VDE","author":"Osmolovskyi S.","year":"2017","unstructured":"S. Osmolovskyi and J. Lienig, \"Physical design challenges and solutions for interposer-based 3d systems,\" in Reliability by Design; 9. ITG\/GMM\/GI-Symposium. VDE, 2017, pp. 1--8."},{"key":"e_1_3_2_1_14_1","first-page":"351","volume-title":"IEEE","author":"Kabir M. A.","year":"2020","unstructured":"M. A. Kabir and Y. Peng, \"Chiplet-package co-design for 2.5 d systems using standard asic cad tools,\" in 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC). IEEE, 2020, pp. 351--356."},{"key":"e_1_3_2_1_15_1","first-page":"1","volume-title":"IEEE","author":"Coskun A.","year":"2018","unstructured":"A. Coskun, F. Eris, A. Joshi, A. B. Kahng, Y. Ma, and V. Srinivas, \"A cross-layer methodology for design and optimization of networks in 2.5 d systems,\" in 2018 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD). IEEE, 2018, pp. 1--8."},{"key":"e_1_3_2_1_16_1","first-page":"1441","volume-title":"Automation & Test in Europe Conference & Exhibition (DATE). IEEE","author":"Eris F.","year":"2018","unstructured":"F. Eris, A. Joshi, A. B. Kahng, Y. Ma, S. Mojumder, and T. Zhang, \"Leveraging thermally-aware chiplet organization in 2.5 d systems to reclaim dark silicon,\" in 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2018, pp. 1441--1446."},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"crossref","unstructured":"W.-H. Liu M.-S. Chang and T.-C. Wang \"Floorplanning and signal assignment for silicon interposer-based 3d ics \" in Proceedings of the 51st Annual Design Automation Conference 2014 pp. 1--6.","DOI":"10.1145\/2593069.2593142"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1007\/s11432-023-3760-8"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2015.71"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/3460227"},{"key":"e_1_3_2_1_21_1","first-page":"1","volume-title":"IEEE Computer Society","author":"Jiang H.","year":"2022","unstructured":"H. Jiang, \"Intel's ponte vecchio gpu: Architecture, systems & software,\" in 2022 IEEE Hot Chips 34 Symposium (HCS). IEEE Computer Society, 2022, pp. 1--29."},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/3508352.3549464"},{"key":"e_1_3_2_1_23_1","article-title":"Floorplet: Performance-aware floorplan framework for chiplet integration","author":"Chen S.","year":"2023","unstructured":"S. Chen, S. Li, Z. Zhuang, S. Zheng, Z. Liang, T.-Y. Ho, B. Yu, and A. L. Sangiovanni-Vincentelli, \"Floorplet: Performance-aware floorplan framework for chiplet integration,\" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2023.","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"e_1_3_2_1_24_1","first-page":"1","article-title":"From 2.5 d to 3d chiplet systems: Investigation of thermal implications with hotspot 7.0,\" in 2022 21st IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (iTherm)","author":"Han J.-H.","year":"2022","unstructured":"J.-H. Han, X. Guo, K. Skadron, and M. R. Stan, \"From 2.5 d to 3d chiplet systems: Investigation of thermal implications with hotspot 7.0,\" in 2022 21st IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (iTherm). IEEE, 2022, pp. 1--6.","journal-title":"IEEE"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1016\/S0026-2692(03)00206-4"},{"key":"e_1_3_2_1_26_1","first-page":"648","article-title":"Optimizing energy efficiency of 3-d multicore systems with stacked dram under power and thermal constraints","volume":"2012","author":"Meng J.","year":"2012","unstructured":"J. Meng, K. Kawakami, and A. K. Coskun, \"Optimizing energy efficiency of 3-d multicore systems with stacked dram under power and thermal constraints,\" in DAC Design Automation Conference 2012, 2012, pp. 648--655.","journal-title":"DAC Design Automation Conference"},{"key":"e_1_3_2_1_27_1","first-page":"1","volume-title":"IEEE","author":"Lin J.-M.","year":"2023","unstructured":"J.-M. Lin, T.-C. Tsai, and R.-T. Shen, \"Routability-driven orientation-aware analytical placement for system in package,\" in 2023 IEEE\/ACM International Conference on Computer Aided Design (ICCAD). IEEE, 2023, pp. 1--8."},{"key":"e_1_3_2_1_28_1","first-page":"1","volume-title":"IEEE","author":"Stow D.","year":"2019","unstructured":"D. Stow, I. Akgun, and Y. Xie, \"Investigation of cost-optimal network-on-chip for passive and active interposer systems,\" in 2019 ACM\/IEEE International Workshop on System Level Interconnect Prediction (SLIP). IEEE, 2019, pp. 1--8."},{"key":"e_1_3_2_1_29_1","first-page":"10","article-title":"Universal chiplet interconnect express (ucie)","author":"Sharma D.","year":"2022","unstructured":"D. Sharma et al., \"Universal chiplet interconnect express (ucie),\" MEPTEC: Road to Chiplets, pp. 10--12, 2022.","journal-title":"MEPTEC: Road to Chiplets"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1109\/MSSC.2019.2910619"},{"key":"e_1_3_2_1_31_1","volume-title":"Advanced cost-driven chiplet interface standard,\" in The 3rd HiPChips Conference at ISCA","author":"Ma K.","year":"2023","unstructured":"K. Ma, \"Introducing acc 1.0: Advanced cost-driven chiplet interface standard,\" in The 3rd HiPChips Conference at ISCA, 2023."},{"key":"e_1_3_2_1_32_1","first-page":"1","volume-title":"IEEE","author":"Lin M.-S.","year":"2016","unstructured":"M.-S. Lin, C.-C. Tsai, C.-H. Hsieh, W.-H. Huang, Y.-C. Chen, S.-C. Yang, C.-M. Fu, H.-J. Zhan, J.-Y. Chien, S.-Y. Li et al., \"A 16nm 256-bit wide 89.6 gbyte\/s total bandwidth in-package interconnect with 0.3 v swing and 0.062 pj\/bit power in info package,\" in 2016 IEEE Hot Chips 28 Symposium (HCS). IEEE, 2016, pp. 1--32."},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2020.3040410"},{"key":"e_1_3_2_1_34_1","volume-title":"Advanced interface bus (aib) specification, revision 2.0.3. Update Date: 2022\/06\/17","year":"2022","unstructured":"Intel. (2022) Advanced interface bus (aib) specification, revision 2.0.3. Update Date: 2022\/06\/17."},{"key":"e_1_3_2_1_35_1","volume-title":"Challenges and opportunities to enable large-scale computing via heterogeneous chiplets,\" arXiv preprint arXiv:2311.16417","author":"Yang Z.","year":"2023","unstructured":"Z. Yang, S. Ji, X. Chen, J. Zhuang, W. Zhang, D. Jani, and P. Zhou, \"Challenges and opportunities to enable large-scale computing via heterogeneous chiplets,\" arXiv preprint arXiv:2311.16417, 2023."},{"key":"e_1_3_2_1_36_1","first-page":"1","volume-title":"Atsim3d: Towards accurate thermal simulator for heterogeneous 3d ic systems considering nonlinear leakage and conductivity,\" in 2024 International Symposium of Electronics Design Automation (ISEDA)","author":"Wang Q.","year":"2024","unstructured":"Q. Wang, T. Zhu, Y. Lin, R. Wang, and R. Huang, \"Atsim3d: Towards accurate thermal simulator for heterogeneous 3d ic systems considering nonlinear leakage and conductivity,\" in 2024 International Symposium of Electronics Design Automation (ISEDA), 2024, pp. 1--6."},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2006.879797"},{"key":"e_1_3_2_1_38_1","unstructured":"\"Comsol Multiphysics \" http:\/\/www.comsol.com\/products\/multiphysics\/."},{"key":"e_1_3_2_1_39_1","unstructured":"\"Cadence Celcius Thermal Solver \" https:\/\/www.cadence.com\/en_US\/home\/tools\/system-analysis\/thermal-solutions\/celsius-thermal-solver.html."},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.883919"},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"crossref","unstructured":"C. Torregiani H. Oprins B. Vandevelde E. Beyne and I. De Wolf \"Compact thermal modeling of hot spots in advanced 3d-stacked ics \" in 2009 11th Electronics Packaging Technology Conference 2009 pp. 131--136.","DOI":"10.1109\/EPTC.2009.5416563"},{"key":"e_1_3_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024748"},{"key":"e_1_3_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2293422"},{"key":"e_1_3_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2193582"},{"key":"e_1_3_2_1_46_1","volume-title":"An inverse natural convection problem of estimating the strength of a heat source,\" International journal of heat and mass transfer","author":"Park H.","unstructured":"H. Park and O. Chung, \"An inverse natural convection problem of estimating the strength of a heat source,\" International journal of heat and mass transfer, vol. 42, no. 23, pp. 4259--4273, 1999."},{"key":"e_1_3_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.1088\/1402-4896\/aba866"},{"key":"e_1_3_2_1_48_1","doi-asserted-by":"publisher","DOI":"10.1145\/3569052.3578923"},{"key":"e_1_3_2_1_49_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.923063"},{"key":"e_1_3_2_1_50_1","first-page":"18311","article-title":"Escaping local optima in global placement","volume":"2402","author":"Xue K.","year":"2024","unstructured":"K. Xue, X. Lin, Y. Shi, S. Kai, S. Xu, and C. Qian, \"Escaping local optima in global placement,\" ArXiv, vol. abs\/2402.18311, 2024. [Online]. Available: https:\/\/api.semanticscholar.org\/CorpusID:268041751","journal-title":"ArXiv"},{"key":"e_1_3_2_1_51_1","first-page":"8024","article-title":"Pytorch: An imperative style, high-performance deep learning library","volume":"32","author":"Paszke A.","year":"2019","unstructured":"A. Paszke, S. Gross, F. Massa, A. Lerer, J. Bradbury, G. Chanan, T. Killeen, Z. Lin, N. Gimelshein, L. Antiga, A. Desmaison, A. Kopf, E. Yang, Z. DeVito, M. Raison, A. Tejani, S. Chilamkurthy, B. Steiner, L. Fang, J. Bai, and S. Chintala, \"Pytorch: An imperative style, high-performance deep learning library,\" in Advances in Neural Information Processing Systems 32, 2019, pp. 8024--8035.","journal-title":"Advances in Neural Information Processing Systems"},{"key":"e_1_3_2_1_52_1","doi-asserted-by":"publisher","DOI":"10.1145\/3292500.3330701"},{"key":"e_1_3_2_1_53_1","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3317803"},{"key":"e_1_3_2_1_54_1","unstructured":"Gurobi Optimization LLC \"Gurobi Optimizer Reference Manual \" 2023. [Online]. Available: https:\/\/www.gurobi.com"},{"key":"e_1_3_2_1_55_1","first-page":"1","volume-title":"IEEE","author":"Lin J.-M.","year":"2018","unstructured":"J.-M. Lin, T.-T. Chen, Y.-F. Chang, W.-Y. Chang, Y.-T. Shyu, Y.-J. Chang, and J.-M. Lu, \"A fast thermal-aware fixed-outline floorplanning methodology based on analytical models,\" in 2018 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD). IEEE, 2018, pp. 1--8."}],"event":{"name":"ICCAD '24: 43rd IEEE\/ACM International Conference on Computer-Aided Design","location":"Newark Liberty International Airport Marriott New York NY USA","acronym":"ICCAD '24","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CAS","IEEE CEDA","IEEE EDS"]},"container-title":["Proceedings of the 43rd IEEE\/ACM International Conference on Computer-Aided Design"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3676536.3676648","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3676536.3676648","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T23:43:56Z","timestamp":1750290236000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3676536.3676648"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,10,27]]},"references-count":54,"alternative-id":["10.1145\/3676536.3676648","10.1145\/3676536"],"URL":"https:\/\/doi.org\/10.1145\/3676536.3676648","relation":{},"subject":[],"published":{"date-parts":[[2024,10,27]]},"assertion":[{"value":"2025-04-09","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}