{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T05:00:18Z","timestamp":1750309218065,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":30,"publisher":"ACM","license":[{"start":{"date-parts":[[2024,10,27]],"date-time":"2024-10-27T00:00:00Z","timestamp":1729987200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2024,10,27]]},"DOI":"10.1145\/3676536.3676657","type":"proceedings-article","created":{"date-parts":[[2025,4,9]],"date-time":"2025-04-09T12:53:56Z","timestamp":1744203236000},"page":"1-8","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Automatic Generation of Cycle-Accurate Timing Models from RTL for Hardware Accelerators"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0009-0000-4514-8867","authenticated-orcid":false,"given":"Yu","family":"Zeng","sequence":"first","affiliation":[{"name":"Princeton University, Princeton, NJ, United States"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6676-9400","authenticated-orcid":false,"given":"Aarti","family":"Gupta","sequence":"additional","affiliation":[{"name":"Princeton University, PRINCETON, NJ, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0837-5443","authenticated-orcid":false,"given":"Sharad","family":"Malik","sequence":"additional","affiliation":[{"name":"Princeton University, PRINCETON, NJ, USA"}]}],"member":"320","published-online":{"date-parts":[[2025,4,9]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"\"VCS - The industry's highest performance simulation solution.\" https:\/\/www.synopsys.com\/verification\/simulation\/vcs.html."},{"key":"e_1_3_2_1_2_1","first-page":"1","volume-title":"Efficiently exploiting low activity factors to accelerate RTL simulation,\" in DAC'2020","author":"Beamer S.","year":"2020","unstructured":"S. Beamer and D. Donofrio, \"Efficiently exploiting low activity factors to accelerate RTL simulation,\" in DAC'2020, pp. 1--6, 2020."},{"volume-title":"The role of cascade, a cycle-based simulation infrastructure, in designing the anton special-purpose supercomputers,\" in DAC'2013","author":"Grossman J.","key":"e_1_3_2_1_3_1","unstructured":"J. Grossman, B. Towles, J. A. Bank, and D. E. Shaw, \"The role of cascade, a cycle-based simulation infrastructure, in designing the anton special-purpose supercomputers,\" in DAC'2013."},{"volume-title":"Accessed on","year":"2023","key":"e_1_3_2_1_4_1","unstructured":"steveicarus, \"iverilog.\" https:\/\/github.com\/steveicarus\/iverilog, 2023. Accessed on March 25, 2023."},{"key":"e_1_3_2_1_5_1","volume-title":"High-speed event-driven RTL compiled simulation,\" in Computer Systems: Architectures, Modeling, and Simulation","author":"Kupriyanov A.","year":"2004","unstructured":"A. Kupriyanov, F. Hannig, and J. Teich, \"High-speed event-driven RTL compiled simulation,\" in Computer Systems: Architectures, Modeling, and Simulation, Springer, 2004."},{"volume-title":"FPGA-accelerated cycle-exact scale-out system simulation in the public cloud,\" ISCA '18","author":"Karandikar S.","key":"e_1_3_2_1_6_1","unstructured":"S. Karandikar and etc., \"FireSim: FPGA-accelerated cycle-exact scale-out system simulation in the public cloud,\" ISCA '18."},{"key":"e_1_3_2_1_7_1","volume-title":"Manticore: Hardware-accelerated RTL simulation with static bulk-synchronous parallelism","author":"Emami M.","year":"2023","unstructured":"M. Emami, S. Kashani, K. Kamahori, M. S. Pourghannad, R. Raj, and J. R. Larus, \"Manticore: Hardware-accelerated RTL simulation with static bulk-synchronous parallelism,\" 2023. arXiv preprint arXiv:2301.09413."},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"crossref","unstructured":"L. Cai and D. Gajski \"Transaction level modeling: an overview \" in Codes+ISSS'2003.","DOI":"10.1145\/944650.944651"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2010.187"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"crossref","unstructured":"Y. Zeng A. Gupta and S. Malik \"Automatic generation of architecture-level models from RTL designs for processors and accelerators \" in DATE'2022.","DOI":"10.23919\/DATE54114.2022.9774527"},{"volume-title":"Chisel: Constructing hardware in a scala embedded language,\" in DAC'2012","author":"Bachrach J.","key":"e_1_3_2_1_12_1","unstructured":"J. Bachrach, H. Vo, B. Richards, Y. Lee, A. Waterman, R. Avi\u017eienis, J. Wawrzynek, and K. Asanovi\u0107, \"Chisel: Constructing hardware in a scala embedded language,\" in DAC'2012."},{"volume-title":"TVM: An automated end-to-end optimizing compiler for deep learning,\" OSDI'18","author":"Chen T.","key":"e_1_3_2_1_13_1","unstructured":"T. Chen, T. Moreau, Z. Jiang, L. Zheng, E. Yan, M. Cowan, H. Shen, L. Wang, Y. Hu, L. Ceze, C. Guestrin, and A. Krishnamurthy, \"TVM: An automated end-to-end optimizing compiler for deep learning,\" OSDI'18."},{"volume-title":"Reusability is FIRRTL ground: Hardware construction languages, compiler frameworks, and transformations,\" in ICCAD'2017","author":"Izraelevitz A.","key":"e_1_3_2_1_14_1","unstructured":"A. Izraelevitz, J. Koenig, P. Li, R. Lin, A. Wang, A. Magyar, D. Kim, C. Schmidt, C. Markley, J. Lawson, and J. Bachrach, \"Reusability is FIRRTL ground: Hardware construction languages, compiler frameworks, and transformations,\" in ICCAD'2017."},{"key":"e_1_3_2_1_15_1","unstructured":"C. Wolf \"Yosys open synthesis suite.\" http:\/\/www.clifford.at\/yosys\/."},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2019.2928962"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/103135.103136"},{"key":"e_1_3_2_1_18_1","first-page":"337","volume-title":"Heidelberg)","author":"De Moura L.","year":"2008","unstructured":"L. De Moura and N. Bj\u00f8rner, \"Z3: An efficient smt solver,\" TACAS'08\/ETAPS'08, (Berlin, Heidelberg), p. 337--340, SpringerVerlag, 2008."},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/2720019"},{"key":"e_1_3_2_1_20_1","volume-title":"Introduction to verilator","author":"Snyder W.","year":"2009","unstructured":"W. Snyder, D. Galbi, and P. Wasson, \"Introduction to verilator,\" 2009."},{"volume-title":"Parallel simulation of loosely timed systemc\/tlm programs: Challenges raised by an industrial case study,\" Electronics","author":"Becker D.","key":"e_1_3_2_1_21_1","unstructured":"D. Becker, M. Moy, and J. Cornet, \"Parallel simulation of loosely timed systemc\/tlm programs: Challenges raised by an industrial case study,\" Electronics, vol. 5, no. 2, 2016."},{"key":"e_1_3_2_1_22_1","unstructured":"\"aes.\" https:\/\/github.com\/yaozhaosh\/chisel-aes Accessed on March'23."},{"key":"e_1_3_2_1_23_1","first-page":"25","article-title":"berkeley-hardfloat.\" https:\/\/github.com\/ucb-bar\/berkeley-hardfloat, 2021","author":"Berkeley","year":"2023","unstructured":"Berkeley, \"berkeley-hardfloat.\" https:\/\/github.com\/ucb-bar\/berkeley-hardfloat, 2021. Accessed on March 25, 2023. Accessed on March 25, 2023.","journal-title":"Accessed on"},{"key":"e_1_3_2_1_24_1","first-page":"25","article-title":"ip-contributions.\" https:\/\/github.com\/freechipsproject\/ip-contributions, 2021","year":"2023","unstructured":"freechipsproject, \"ip-contributions.\" https:\/\/github.com\/freechipsproject\/ip-contributions, 2021. Accessed on March 25, 2023. Accessed on March 25, 2023.","journal-title":"Accessed on"},{"key":"e_1_3_2_1_25_1","first-page":"25","article-title":"sodla.\" https:\/\/github.com\/soDLA-publishment\/soDLA, 2019","year":"2023","unstructured":"\"sodla.\" https:\/\/github.com\/soDLA-publishment\/soDLA, 2019. Accessed on March 25, 2023. Accessed on March 25, 2023.","journal-title":"Accessed on"},{"volume-title":"Accessed on","year":"2023","key":"e_1_3_2_1_26_1","unstructured":"ucb bar, \"riscv-mini.\" https:\/\/github.com\/ucb-bar\/riscv-mini, 2023. Accessed on March 25, 2023."},{"volume-title":"Accelerating RTL simulation with GPUs,\" in ICCAD'2011","author":"Qian H.","key":"e_1_3_2_1_27_1","unstructured":"H. Qian and Y. Deng, \"Accelerating RTL simulation with GPUs,\" in ICCAD'2011."},{"key":"e_1_3_2_1_28_1","first-page":"2011","article-title":"Gate-level simulation with gpu computing","volume":"16","author":"Chatterjee D.","unstructured":"D. Chatterjee, A. Deorio, and V. Bertacco, \"Gate-level simulation with gpu computing,\" ACM Trans. Des. Autom. Electron. Syst., vol. 16, jun 2011.","journal-title":"ACM Trans. Des. Autom. Electron. Syst."},{"key":"e_1_3_2_1_29_1","volume-title":"System Design with SystemC","author":"Thorsten Gr\u00f6tker G. M. S. S.","year":"2007","unstructured":"G. M. S. S. Thorsten Gr\u00f6tker, Stan Liao, System Design with SystemC. New York, NY: Springer, 1st ed., 2007.","edition":"1"},{"volume-title":"Instruction-Level Abstraction: A uniform specification for system-on-chip (SoC) verification,\" TODAES'2018","author":"Huang B.-Y.","key":"e_1_3_2_1_30_1","unstructured":"B.-Y. Huang, H. Zhang, P. Subramanyan, Y. Vizel, A. Gupta, and S. Malik, \"Instruction-Level Abstraction: A uniform specification for system-on-chip (SoC) verification,\" TODAES'2018."},{"volume-title":"Approximate-timed transactional level modeling for mpsoc exploration: A network-on-chip case study,\" in DSD'2009","author":"Guerre A.","key":"e_1_3_2_1_31_1","unstructured":"A. Guerre, N. Ventroux, R. David, and A. Merigot, \"Approximate-timed transactional level modeling for mpsoc exploration: A network-on-chip case study,\" in DSD'2009."}],"event":{"name":"ICCAD '24: 43rd IEEE\/ACM International Conference on Computer-Aided Design","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CAS","IEEE CEDA","IEEE EDS"],"location":"Newark Liberty International Airport Marriott New York NY USA","acronym":"ICCAD '24"},"container-title":["Proceedings of the 43rd IEEE\/ACM International Conference on Computer-Aided Design"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3676536.3676657","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3676536.3676657","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T23:43:57Z","timestamp":1750290237000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3676536.3676657"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,10,27]]},"references-count":30,"alternative-id":["10.1145\/3676536.3676657","10.1145\/3676536"],"URL":"https:\/\/doi.org\/10.1145\/3676536.3676657","relation":{},"subject":[],"published":{"date-parts":[[2024,10,27]]},"assertion":[{"value":"2025-04-09","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}