{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T05:00:18Z","timestamp":1750309218164,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":39,"publisher":"ACM","license":[{"start":{"date-parts":[[2024,10,27]],"date-time":"2024-10-27T00:00:00Z","timestamp":1729987200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2024,10,27]]},"DOI":"10.1145\/3676536.3676668","type":"proceedings-article","created":{"date-parts":[[2025,4,9]],"date-time":"2025-04-09T12:53:56Z","timestamp":1744203236000},"page":"1-9","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["CircuitSeer: RTL Post-PnR Delay Prediction via Coupling Functional and Structural Representation"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-5819-1773","authenticated-orcid":false,"given":"Sanjay","family":"Gandham","sequence":"first","affiliation":[{"name":"University of Central Florida, Orlando, United States"}]},{"ORCID":"https:\/\/orcid.org\/0009-0003-9697-9144","authenticated-orcid":false,"given":"Joe","family":"Walston","sequence":"additional","affiliation":[{"name":"Synopsys, Inc., Sunnyvale, USA"}]},{"ORCID":"https:\/\/orcid.org\/0009-0002-6944-0197","authenticated-orcid":false,"given":"Sourav","family":"Samanta","sequence":"additional","affiliation":[{"name":"Synopsys, Inc., Sunnyvale, USA"}]},{"ORCID":"https:\/\/orcid.org\/0009-0005-9279-9220","authenticated-orcid":false,"given":"Lingxiang","family":"Yin","sequence":"additional","affiliation":[{"name":"University of Central Florida, Orlando, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4391-2774","authenticated-orcid":false,"given":"Hao","family":"Zheng","sequence":"additional","affiliation":[{"name":"University of Central Florida, Orlando, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3225-4406","authenticated-orcid":false,"given":"Mingjie","family":"Lin","sequence":"additional","affiliation":[{"name":"University of Central Florida, Orlando, USA"}]},{"ORCID":"https:\/\/orcid.org\/0009-0002-5305-2966","authenticated-orcid":false,"given":"Stelios","family":"Diamantidis","sequence":"additional","affiliation":[{"name":"Synopsys, Inc., Sunnyvale, USA"}]}],"member":"320","published-online":{"date-parts":[[2025,4,9]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/3470496.3527444"},{"key":"e_1_3_2_1_2_1","first-page":"1","volume-title":"Proceedings of the 41st IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)","author":"Sengupta Prianka","year":"2022","unstructured":"Prianka Sengupta, Aakash Tyagi, Yiran Chen, and Jiang Hu. How good is your verilog rtl code? a quick answer from machine learning. In Proceedings of the 41st IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), pages 1--9. IEEE, 2022."},{"key":"e_1_3_2_1_3_1","first-page":"1","volume-title":"Proceedings of the 42nd IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)","author":"Agiza Ahmed","year":"2023","unstructured":"Ahmed Agiza, Rajarshi Roy, Teodor Dumitru Ene, Saad Godil, Sherief Reda, and Bryan Catanzaro. Graphsym: Graph physical synthesis model. In Proceedings of the 42nd IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), pages 1--9. IEEE, 2023."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD57390.2023.10323951"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/MLCAD58807.2023.10299879"},{"key":"e_1_3_2_1_6_1","volume-title":"Chip placement with deep reinforcement learning. In arXiv preprint arXiv:2004.10746","author":"Mirhoseini Azalia","year":"2020","unstructured":"Azalia Mirhoseini, Anna Goldie, Mustafa Yazgan, Joe Jiang, Ebrahim Songhori, Shen Wang, Young-Joon Lee, Eric Johnson, Omkar Pathak, Sungmin Bae, et al. Chip placement with deep reinforcement learning. In arXiv preprint arXiv:2004.10746, 2020."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18074.2021.9586094"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP54787.2022.00013"},{"key":"e_1_3_2_1_9_1","volume-title":"Bulls-eye: Active few-shot learning guided logic synthesis","author":"Chowdhury Animesh Basak","year":"2022","unstructured":"Animesh Basak Chowdhury, Benjamin Tan, Ryan Carey, Tushit Jain, Ramesh Karri, and Siddharth Garg. Bulls-eye: Active few-shot learning guided logic synthesis. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. IEEE, 2022."},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD45719.2019.8942145"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/DAC56929.2023.10248008"},{"key":"e_1_3_2_1_12_1","volume-title":"Graph neural networks exponentially lose expressive power for node classification. In arXiv preprint arXiv:1905.10947","author":"Oono Kenta","year":"2019","unstructured":"Kenta Oono and Taiji Suzuki. Graph neural networks exponentially lose expressive power for node classification. In arXiv preprint arXiv:1905.10947, 2019."},{"key":"e_1_3_2_1_13_1","volume-title":"Semi-supervised classification with graph convolutional networks. arXiv preprint arXiv:1609.02907","author":"Kipf Thomas N","year":"2016","unstructured":"Thomas N Kipf and Max Welling. Semi-supervised classification with graph convolutional networks. arXiv preprint arXiv:1609.02907, 2016."},{"key":"e_1_3_2_1_14_1","volume-title":"Graph attention networks. In arXiv preprint arXiv:1710.10903","author":"Veli\u010dkovi\u0107 Petar","year":"2017","unstructured":"Petar Veli\u010dkovi\u0107, Guillem Cucurull, Arantxa Casanova, Adriana Romero, Pietro Lio, and Yoshua Bengio. Graph attention networks. In arXiv preprint arXiv:1710.10903, 2017."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-SoC.2019.8920342"},{"key":"e_1_3_2_1_16_1","first-page":"671","volume-title":"Proceedings of the 26th Asia and South Pacific Design Automation Conference (ASP-DAC)","author":"Xie Zhiyao","year":"2021","unstructured":"Zhiyao Xie, Rongjian Liang, Xiaoqing Xu, Jiang Hu, Yixiao Duan, and Yiran Chen. Net2: A graph attention network method customized for pre-placement net length estimation. In Proceedings of the 26th Asia and South Pacific Design Automation Conference (ASP-DAC), pages 671--677. IEEE, 2021."},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/3508352.3561094"},{"key":"e_1_3_2_1_18_1","volume-title":"International Workshop for Logic Synthesis (IWLS). IEEE","author":"Albrecht Christoph","year":"2005","unstructured":"Christoph Albrecht. Iwls 2005 benchmarks. In International Workshop for Logic Synthesis (IWLS). IEEE, 2005."},{"key":"e_1_3_2_1_19_1","unstructured":"Open cores. https:\/\/opencores.org\/. Accessed: 2024-03-08."},{"key":"e_1_3_2_1_20_1","unstructured":"Synopsys Inc. Fusion compiler for simply better ppa. https:\/\/www.synopsys.com\/implementation-and-signoff\/physicalimplementation\/fusion-compiler.html. Accessed: 2024-03-08."},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18072.2020.9218643"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18072.2020.9218515"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18074.2021.9586138"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/3508352.3561093"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/3489517.3530597"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/DAC56929.2023.10247828"},{"key":"e_1_3_2_1_27_1","volume-title":"How powerful are graph neural networks? In arXiv preprint arXiv:1810.00826","author":"Xu Keyulu","year":"2018","unstructured":"Keyulu Xu, Weihua Hu, Jure Leskovec, and Stefanie Jegelka. How powerful are graph neural networks? In arXiv preprint arXiv:1810.00826, 2018."},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/3508352.3561095"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1145\/3394885.3431545"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/3489517.3530410"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD57390.2023.10323798"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1007\/s00521-023-08346-x"},{"key":"e_1_3_2_1_33_1","volume-title":"ACM","author":"Vaswani Ashish","year":"2017","unstructured":"Ashish Vaswani, Noam Shazeer, Niki Parmar, Jakob Uszkoreit, Llion Jones, Aidan N Gomez, \u0141ukasz Kaiser, and Illia Polosukhin. Attention is all you need. In Advances in neural information processing systems (NeurIPS). ACM, 2017."},{"key":"e_1_3_2_1_34_1","first-page":"1","volume-title":"Proceedings of the 41st IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)","author":"Nath Siddhartha","year":"2022","unstructured":"Siddhartha Nath, Geraldo Pradipta, Corey Hu, Tian Yang, Brucek Khailany, and Haoxing Ren. Transsizer: A novel transformer-based fast gate sizer. In Proceedings of the 41st IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), pages 1--9. IEEE, 2022."},{"key":"e_1_3_2_1_35_1","volume-title":"Adam: A method for stochastic optimization. In arXiv preprint arXiv:1412.6980","author":"Kingma Diederik P","year":"2014","unstructured":"Diederik P Kingma and Jimmy Ba. Adam: A method for stochastic optimization. In arXiv preprint arXiv:1412.6980, 2014."},{"key":"e_1_3_2_1_36_1","volume-title":"Fast graph representation learning with pytorch geometric. In arXiv preprint arXiv:1903.02428","author":"Fey Matthias","year":"2019","unstructured":"Matthias Fey and Jan Eric Lenssen. Fast graph representation learning with pytorch geometric. In arXiv preprint arXiv:1903.02428, 2019."},{"key":"e_1_3_2_1_37_1","volume-title":"International Test Synthesis Workshop (ITSW). IEEE","author":"Davidson Scott","year":"1999","unstructured":"Scott Davidson. Characteristics of the itc'99 benchmark circuits. In International Test Synthesis Workshop (ITSW). IEEE, 1999."},{"key":"e_1_3_2_1_38_1","volume-title":"Proceedings of the 21st Austrian Workshop on Microelectronics (Austrochip). IEEE","author":"Wolf Clifford","year":"2013","unstructured":"Clifford Wolf, Johann Glaser, and Johannes Kepler. Yosys-a free verilog synthesis suite. In Proceedings of the 21st Austrian Workshop on Microelectronics (Austrochip). IEEE, 2013."},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1145\/2939672.2939785"}],"event":{"name":"ICCAD '24: 43rd IEEE\/ACM International Conference on Computer-Aided Design","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CAS","IEEE CEDA","IEEE EDS"],"location":"Newark Liberty International Airport Marriott New York NY USA","acronym":"ICCAD '24"},"container-title":["Proceedings of the 43rd IEEE\/ACM International Conference on Computer-Aided Design"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3676536.3676668","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3676536.3676668","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T23:43:57Z","timestamp":1750290237000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3676536.3676668"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,10,27]]},"references-count":39,"alternative-id":["10.1145\/3676536.3676668","10.1145\/3676536"],"URL":"https:\/\/doi.org\/10.1145\/3676536.3676668","relation":{},"subject":[],"published":{"date-parts":[[2024,10,27]]},"assertion":[{"value":"2025-04-09","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}