{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,19]],"date-time":"2026-06-19T02:49:19Z","timestamp":1781837359076,"version":"3.54.5"},"publisher-location":"New York, NY, USA","reference-count":40,"publisher":"ACM","license":[{"start":{"date-parts":[[2024,10,27]],"date-time":"2024-10-27T00:00:00Z","timestamp":1729987200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2024,10,27]]},"DOI":"10.1145\/3676536.3676755","type":"proceedings-article","created":{"date-parts":[[2025,4,9]],"date-time":"2025-04-09T13:21:20Z","timestamp":1744204880000},"page":"1-9","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":6,"title":["Single Instruction Isolation for RISC-V Vector Test Failures"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0009-0007-3275-4797","authenticated-orcid":false,"given":"Manfred","family":"Schlaegl","sequence":"first","affiliation":[{"name":"Institute for Complex Systems, Johannes Kepler University, Linz, Austria"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1490-6175","authenticated-orcid":false,"given":"Daniel","family":"Grosse","sequence":"additional","affiliation":[{"name":"Institute for Complex Systems, Johannes Kepler University, Linz, Austria"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2025,4,9]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"2021. RISC-V Compliance Task Group. https:\/\/github.com\/riscv\/riscv-compliance."},{"key":"e_1_3_2_1_2_1","unstructured":"2021. RISC-V Torture Test Generator. https:\/\/github.com\/ucb-bar\/riscv-torture."},{"key":"e_1_3_2_1_3_1","unstructured":"2022. RISC-V V vector extension. https:\/\/github.com\/riscv\/riscv-v-spec."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","unstructured":"2023. IEEE Standard for Standard SystemC Language Reference Manual. 10.1109\/IEEESTD.2023.10246125","DOI":"10.1109\/IEEESTD.2023.10246125"},{"key":"e_1_3_2_1_5_1","unstructured":"2024. FORCE-RISCV RISC-V Instruction Sequence Generator (ISG). https:\/\/github.com\/openhwgroup\/force-riscv."},{"key":"e_1_3_2_1_6_1","unstructured":"2024. QEMU A generic and open source machine emulator and virtualizer. https:\/\/www.qemu.org."},{"key":"e_1_3_2_1_7_1","unstructured":"2024. RISC-V Architecture Test SIG. https:\/\/github.com\/riscv-non-isa\/riscv-arch-test."},{"key":"e_1_3_2_1_8_1","unstructured":"2024. RISC-V Formal Verification Framework. https:\/\/github.com\/YosysHQ\/riscv-formal."},{"key":"e_1_3_2_1_9_1","unstructured":"2024. RISCV-DV. https:\/\/github.com\/google\/riscv-dv."},{"key":"e_1_3_2_1_10_1","unstructured":"2024. RISCV Sail Model. https:\/\/github.com\/rems-project\/sail-riscv."},{"key":"e_1_3_2_1_11_1","unstructured":"2024. riscvOVPsim Imperas RISC-VInstruction Set Simulator (ISS). https:\/\/www.imperas.com\/riscvovpsim-free-imperas-risc-v-instruction-set-simulator."},{"key":"e_1_3_2_1_12_1","unstructured":"2024. Siemens EDA Questa Formal Verification Apps. https:\/\/eda.sw.siemens.com\/en-US\/ic\/questa\/formal-verification."},{"key":"e_1_3_2_1_13_1","unstructured":"2024. Spike RISC-V ISA Simulator. https:\/\/github.com\/riscv\/riscv-isa-sim."},{"key":"e_1_3_2_1_14_1","volume-title":"Genesys-Pro: innovations in test program generation for functional processor verification","author":"Adir Allon","year":"2004","unstructured":"Allon Adir, Eli Almog, Laurent Fournier, Eitan Marcus, Michal Rimon, Michael Vinov, and Avi Ziv. 2004. Genesys-Pro: innovations in test program generation for functional processor verification. IEEE Design & Test of Comp. (2004), 84--93."},{"key":"e_1_3_2_1_15_1","volume-title":"Early Verification of ISA Extension Specifications Using Deep Reinforcement Learning. In ACM Great Lakes Symposium on VLSI. 297--302","author":"Bruns Niklas","year":"2020","unstructured":"Niklas Bruns, Daniel Gro\u00dfe, and Rolf Drechsler. 2020. Early Verification of ISA Extension Specifications Using Deep Reinforcement Learning. In ACM Great Lakes Symposium on VLSI. 297--302."},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"crossref","unstructured":"Brian Campbell and Ian Stark. 2014. Randomised Testing of a Microprocessor Model Using SMT-Solver State Generation. In Formal Methods for Industrial Critical Systems. 185--199.","DOI":"10.1007\/978-3-319-10702-8_13"},{"key":"e_1_3_2_1_17_1","volume-title":"MicroTESK: Specification-Based Tool for Constructing Test Program Generators. In Haifa Verification Conference. 217--220","author":"Chupilko Mikhail","year":"2017","unstructured":"Mikhail Chupilko, Alexander Kamkin, Artem Kotsynyak, and Andrei Tatarnikov. 2017. MicroTESK: Specification-Based Tool for Constructing Test Program Generators. In Haifa Verification Conference. 217--220."},{"key":"e_1_3_2_1_18_1","volume-title":"Eshan Singh, Clark W. Barrett, Subhasish Mitra, Wolfgang Ecker, Dominik Stoffel, and Wolfgang Kunz.","author":"Devarajegowda Keerthikumara","year":"2020","unstructured":"Keerthikumara Devarajegowda, Mohammad Rahmani Fadiheh, Eshan Singh, Clark W. Barrett, Subhasish Mitra, Wolfgang Ecker, Dominik Stoffel, and Wolfgang Kunz. 2020. Gap-free Processor Verification by S2QED and Property Generation. In Design, Automation and Test in Europe. 526--531."},{"key":"e_1_3_2_1_19_1","volume-title":"Present and Future. In International Conference on Supercomputing. 425--432","author":"Espasa Roger","unstructured":"Roger Espasa, Mateo Valero, and James E. Smith. 1998. Vector Architectures: Past, Present and Future. In International Conference on Supercomputing. 425--432."},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/775832.775907"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/PROC.1966.5273"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18072.2020.9218629"},{"key":"e_1_3_2_1_23_1","volume-title":"Enhanced Virtual Prototyping: Featuring RISC-V Case Studies","author":"Herdt Vladimir","unstructured":"Vladimir Herdt, Daniel Gro\u00dfe, and Rolf Drechsler. 2020. Enhanced Virtual Prototyping: Featuring RISC-V Case Studies. Springer."},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"crossref","unstructured":"Vladimir Herdt Daniel Gro\u00dfe and Rolf Drechsler. 2020. Towards Specification and Testing of RISC-V ISA Compliance. In Design Automation and Test in Europe. 995--998.","DOI":"10.23919\/DATE48585.2020.9116193"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"crossref","unstructured":"Vladimir Herdt Daniel Gro\u00dfe Eyck Jentzsch and Rolf Drechsler. 2020. Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study. In Forum on Specification and Design Languages. 1--7.","DOI":"10.1109\/FDL50818.2020.9232941"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"crossref","unstructured":"Vladimir Herdt Daniel Gro\u00dfe Hoang M. Le and Rolf Drechsler. 2019. Verifying Instruction Set Simulators using Coverage-guided Fuzzing. In Design Automation and Test in Europe. 360--365.","DOI":"10.23919\/DATE.2019.8714912"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/SP40001.2021.00103"},{"key":"e_1_3_2_1_28_1","volume-title":"Feedback-Based Coverage Directed Test Generation: An Industrial Evaluation. In Haifa Verification Conference. 112--128","author":"Ioannides Charalambos","year":"2011","unstructured":"Charalambos Ioannides, Geoff Barrett, and Kerstin Eder. 2011. Feedback-Based Coverage Directed Test Generation: An Industrial Evaluation. In Haifa Verification Conference. 112--128."},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2022.3226709"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"crossref","unstructured":"Yoav Katz Michal Rimon and Avi Ziv. 2012. Generating instruction streams using abstract CSP. In Design Automation and Test in Europe. 15--20.","DOI":"10.1109\/DATE.2012.6176425"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/3453688.3461497"},{"key":"e_1_3_2_1_32_1","volume-title":"Testing CPU Emulators. In International Symposium on Software Testing and Analysis. 261--272","author":"Martignoni Lorenzo","year":"2009","unstructured":"Lorenzo Martignoni, Roberto Paleari, Giampaolo Fresi Roglia, and Danilo Bruschi. 2009. Testing CPU Emulators. In International Symposium on Software Testing and Analysis. 261--272."},{"key":"e_1_3_2_1_33_1","volume-title":"GUI-VP Kit: A RISC-V VP Meets Linux Graphics - Enabling Interactive Graphical Application Development. In ACM Great Lakes Symposium on VLSI. 599--605","author":"Schl\u00e4gl Manfred","year":"2023","unstructured":"Manfred Schl\u00e4gl and Daniel Gro\u00dfe. 2023. GUI-VP Kit: A RISC-V VP Meets Linux Graphics - Enabling Interactive Graphical Application Development. In ACM Great Lakes Symposium on VLSI. 599--605."},{"key":"e_1_3_2_1_34_1","unstructured":"Manfred Schl\u00e4gl and Daniel Gro\u00dfe. 2024. Bounded Load\/Stores in Grammar-based Code Generation for Testing the RISC-V Vector Extension. In RISC-V Summit Europe."},{"key":"e_1_3_2_1_35_1","volume-title":"Workshop on Open-Source Design Automation.","author":"Schl\u00e4gl Manfred","year":"2024","unstructured":"Manfred Schl\u00e4gl, Christoph Hazott, and Daniel Gro\u00dfe. 2024. RISC-V VP++: Next Generation Open-Source Virtual Prototype. In Workshop on Open-Source Design Automation."},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"crossref","unstructured":"Manfred Schl\u00e4gl Moritz Stockinger and Daniel Gro\u00dfe. 2024. A RISC-V \"V\" VP: Unlocking Vector Processing for Evaluation at the System Level. In Design Automation and Test in Europe. 1--6.","DOI":"10.23919\/DATE58400.2024.10546838"},{"key":"e_1_3_2_1_37_1","volume-title":"Logic Bug Detection and Localization Using Symbolic Quick Error Detection","author":"Singh Eshan","year":"2018","unstructured":"Eshan Singh, David Lin, Clark W. Barrett, and Subhasish Mitra. 2018. Logic Bug Detection and Localization Using Symbolic Quick Error Detection. IEEE Transactions on Computer Aided Design of Circuits and Systems (2018)."},{"key":"e_1_3_2_1_38_1","volume-title":"A-QED Verification of Hardware Accelerators. In Design Automation Conf. 1--6.","author":"Singh Eshan","year":"2020","unstructured":"Eshan Singh, Florian Lonsing, Saranyu Chattopadhyay, Maxwell Strange, Peng Wei, Xiaofan Zhang, Yuan Zhou, Deming Chen, Jason Cong, Priyanka Raina, Zhiru Zhang, Clark W. Barrett, and Subhasish Mitra. 2020. A-QED Verification of Hardware Accelerators. In Design Automation Conf. 1--6."},{"key":"e_1_3_2_1_39_1","volume-title":"The RISC-V Instruction Set Manual","author":"Waterman Andrew","unstructured":"Andrew Waterman and Krste Asanovi\u0107. 2019. The RISC-V Instruction Set Manual; Volume I: Unprivileged ISA. SiFive Inc. and UC Berkeley."},{"key":"e_1_3_2_1_40_1","volume-title":"The RISC-V Instruction Set Manual","author":"Waterman Andrew","unstructured":"Andrew Waterman and Krste Asanovi\u0107. 2019. The RISC-V Instruction Set Manual; Volume II: Privileged Architecture. SiFive Inc. and UC Berkeley."}],"event":{"name":"ICCAD '24: 43rd IEEE\/ACM International Conference on Computer-Aided Design","location":"Newark Liberty International Airport Marriott New York NY USA","acronym":"ICCAD '24","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CAS","IEEE CEDA","IEEE EDS"]},"container-title":["Proceedings of the 43rd IEEE\/ACM International Conference on Computer-Aided Design"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3676536.3676755","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3676536.3676755","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T23:43:58Z","timestamp":1750290238000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3676536.3676755"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,10,27]]},"references-count":40,"alternative-id":["10.1145\/3676536.3676755","10.1145\/3676536"],"URL":"https:\/\/doi.org\/10.1145\/3676536.3676755","relation":{},"subject":[],"published":{"date-parts":[[2024,10,27]]},"assertion":[{"value":"2025-04-09","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}