{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,28]],"date-time":"2026-03-28T08:48:14Z","timestamp":1774687694370,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":53,"publisher":"ACM","license":[{"start":{"date-parts":[[2024,10,27]],"date-time":"2024-10-27T00:00:00Z","timestamp":1729987200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2024,10,27]]},"DOI":"10.1145\/3676536.3676775","type":"proceedings-article","created":{"date-parts":[[2025,4,9]],"date-time":"2025-04-09T12:53:56Z","timestamp":1744203236000},"page":"1-7","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":18,"title":["RTLRewriter: Methodologies for Large Models aided RTL Code Optimization"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-7994-6290","authenticated-orcid":false,"given":"Xufeng","family":"Yao","sequence":"first","affiliation":[{"name":"CUHK, HongKong, Hong Kong"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8966-5938","authenticated-orcid":false,"given":"Yiwen","family":"Wang","sequence":"additional","affiliation":[{"name":"Huawei, Hong Kong, Hong Kong"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1669-5954","authenticated-orcid":false,"given":"Xing","family":"Li","sequence":"additional","affiliation":[{"name":"Huawei, Hong Kong, Hong Kong"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9242-143X","authenticated-orcid":false,"given":"Yingzhao","family":"Lian","sequence":"additional","affiliation":[{"name":"Huawei, Hong Kong, Hong Kong"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9363-5325","authenticated-orcid":false,"given":"Ran","family":"Chen","sequence":"additional","affiliation":[{"name":"Huawei, Hong Kong, Hong Kong"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1054-5501","authenticated-orcid":false,"given":"Lei","family":"Chen","sequence":"additional","affiliation":[{"name":"Huawei, Hong Kong, Hong Kong"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2236-8784","authenticated-orcid":false,"given":"Mingxuan","family":"Yuan","sequence":"additional","affiliation":[{"name":"Huawei, Hong Kong, Hong Kong"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9359-9571","authenticated-orcid":false,"given":"Hong","family":"Xu","sequence":"additional","affiliation":[{"name":"Huawei, Hong Kong, Hong Kong"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6406-4810","authenticated-orcid":false,"given":"Bei","family":"Yu","sequence":"additional","affiliation":[{"name":"Chinese University of HongKong, Hong Kong, Hong Kong Special Administrative Region of China"}]}],"member":"320","published-online":{"date-parts":[[2025,4,9]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"Yosys-a free verilog synthesis suite,\" in Proceedings of the 21st Austrian Workshop on Microelectronics (Austrochip)","author":"Wolf C.","year":"2013","unstructured":"C. Wolf, J. Glaser, and J. Kepler, \"Yosys-a free verilog synthesis suite,\" in Proceedings of the 21st Austrian Workshop on Microelectronics (Austrochip), vol. 97, 2013."},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.739059"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/103135.103136"},{"key":"e_1_3_2_1_4_1","first-page":"68","volume-title":"IEEE","author":"Chen D.","year":"2004","unstructured":"D. Chen and J. Cong, \"Register binding and port assignment for multiplexer optimization,\" in ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No. 04EX753). IEEE, 2004, pp. 68--73."},{"key":"e_1_3_2_1_5_1","unstructured":"P. Pi\u0161teka K. Jelemensk\u00e1 and M. Koles\u00e1r \"Reduction of multiplexer trees using modified lookup table.\""},{"key":"e_1_3_2_1_6_1","first-page":"121","volume-title":"IEEE","author":"Wang Z.","year":"2023","unstructured":"Z. Wang, H. You, J. Wang, M. Liu, Y. Su, and Y. Zhang, \"Optimization of multiplexer combination in rtl logic synthesis,\" in 2023 International Symposium of Electronics Design Automation (ISEDA). IEEE, 2023, pp. 121--125."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"crossref","unstructured":"J. Cocke \"Global common subexpression elimination \" in Proceedings of a symposium on Compiler optimization 1970 pp. 20--24.","DOI":"10.1145\/800028.808480"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/773473.178256"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/504709.504710"},{"key":"e_1_3_2_1_10_1","first-page":"149","volume-title":"IEEE","author":"Darte A.","year":"1999","unstructured":"A. Darte, \"On the complexity of loop fusion,\" in 1999 International Conference on Parallel Architectures and Compilation Techniques (Cat. No. PR00425). IEEE, 1999, pp. 149--157."},{"key":"e_1_3_2_1_11_1","first-page":"133","volume-title":"Highly pipelined asynchronous fpgas,\" in proceedings of the 2004 ACM\/SIGDA 12th International symposium on field programmable gate arrays","author":"Teifel J.","year":"2004","unstructured":"J. Teifel and R. Manohar, \"Highly pipelined asynchronous fpgas,\" in proceedings of the 2004 ACM\/SIGDA 12th International symposium on field programmable gate arrays, 2004, pp. 133--142."},{"key":"e_1_3_2_1_12_1","volume-title":"Synthesis of finite state machines: functional optimization","author":"Kam T.","year":"2013","unstructured":"T. Kam, T. Villa, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, Synthesis of finite state machines: functional optimization. Springer Science & Business Media, 2013."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.5555\/2462879"},{"key":"e_1_3_2_1_14_1","first-page":"620","volume-title":"IEEE","author":"Shelar R. S.","year":"1999","unstructured":"R. S. Shelar, M. P. Desai, and H. Narayanan, \"Decomposition of finite state machines for area, delay minimization,\" in Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No. 99CB37040). IEEE, 1999, pp. 620--625."},{"key":"e_1_3_2_1_15_1","first-page":"41","volume-title":"Efficient multi-ported memories for fpgas,\" in Proceedings of the 18th annual ACM\/SIGDA international symposium on Field programmable gate arrays","author":"La Forest C. E.","year":"2010","unstructured":"C. E. La Forest and J. G. Steffan, \"Efficient multi-ported memories for fpgas,\" in Proceedings of the 18th annual ACM\/SIGDA international symposium on Field programmable gate arrays, 2010, pp. 41--50."},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/3373376.3378482"},{"key":"e_1_3_2_1_17_1","first-page":"179","volume-title":"A new approach to automatic memory banking using trace-based address mining,\" in Proceedings of the 2017 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays","author":"Zhou Y.","year":"2017","unstructured":"Y. Zhou, K. M. Al-Hawaj, and Z. Zhang, \"A new approach to automatic memory banking using trace-based address mining,\" in Proceedings of the 2017 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017, pp. 179--188."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2957455"},{"key":"e_1_3_2_1_19_1","first-page":"221","volume-title":"Synthesis of pipelined memory access controllers for streamed data applications on fpga-based computing engines,\" in Proceedings of the 14th international symposium on Systems synthesis","author":"Park J.","year":"2001","unstructured":"J. Park and P. C. Diniz, \"Synthesis of pipelined memory access controllers for streamed data applications on fpga-based computing engines,\" in Proceedings of the 14th international symposium on Systems synthesis, 2001, pp. 221--226."},{"key":"e_1_3_2_1_20_1","volume-title":"Bayraktaroglu et al., \"Chipnemo: Domain-adapted llms for chip design,\" arXiv preprint arXiv:2311.00176","author":"Liu M.","year":"2023","unstructured":"M. Liu, T.-D. Ene, R. Kirby, C. Cheng, N. Pinckney, R. Liang, J. Alben, H. Anand, S. Banerjee, I. Bayraktaroglu et al., \"Chipnemo: Domain-adapted llms for chip design,\" arXiv preprint arXiv:2311.00176, 2023."},{"key":"e_1_3_2_1_21_1","first-page":"1","volume-title":"IEEE","author":"Blocklove J.","year":"2023","unstructured":"J. Blocklove, S. Garg, R. Karri, and H. Pearce, \"Chip-chat: Challenges and opportunities in conversational hardware design,\" in 2023 ACM\/IEEE 5th Workshop on Machine Learning for CAD (MLCAD). IEEE, 2023, pp. 1--6."},{"key":"e_1_3_2_1_22_1","first-page":"1","volume-title":"IEEE","author":"Fu Y.","year":"2023","unstructured":"Y. Fu, Y. Zhang, Z. Yu, S. Li, Z. Ye, C. Li, C. Wan, and Y. C. Lin, \"Gpt4aigchip: Towards next-generation ai accelerator design automation via large language models,\" in 2023 IEEE\/ACM International Conference on Computer Aided Design (ICCAD). IEEE, 2023, pp. 1--9."},{"key":"e_1_3_2_1_23_1","volume-title":"Data4aigchip: An automated data generation and validation flow for llm-assisted hardware design","author":"Zhang Y.","year":"2024","unstructured":"Y. Zhang, Y. Fu, Z. Yu, K. Zhao, C. Wan, C. Li, and Y. C. Lin, \"Data4aigchip: An automated data generation and validation flow for llm-assisted hardware design,\" 2024."},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2024.3383347"},{"key":"e_1_3_2_1_25_1","volume-title":"Verigen: A large language model for verilog code generation,\" arXiv preprint arXiv:2308.00708","author":"Thakur S.","year":"2023","unstructured":"S. Thakur, B. Ahmad, H. Pearce, B. Tan, B. Dolan-Gavitt, R. Karri, and S. Garg, \"Verigen: A large language model for verilog code generation,\" arXiv preprint arXiv:2308.00708, 2023."},{"key":"e_1_3_2_1_26_1","volume-title":"Rtlcoder: Outperforming gpt-3.5 in design rtl generation with our open-source dataset and lightweight solution,\" arXiv preprint arXiv:2312.08617","author":"Liu S.","year":"2023","unstructured":"S. Liu, W. Fang, Y. Lu, Q. Zhang, H. Zhang, and Z. Xie, \"Rtlcoder: Outperforming gpt-3.5 in design rtl generation with our open-source dataset and lightweight solution,\" arXiv preprint arXiv:2312.08617, 2023."},{"key":"e_1_3_2_1_27_1","volume-title":"Make every move count: Llm-based high-quality rtl code generation using mcts,\" arXiv preprint arXiv:2402.03289","author":"DeLorenzo M.","year":"2024","unstructured":"M. DeLorenzo, A. B. Chowdhury, V. Gohil, S. Thakur, R. Karri, S. Garg, and J. Rajendran, \"Make every move count: Llm-based high-quality rtl code generation using mcts,\" arXiv preprint arXiv:2402.03289, 2024."},{"key":"e_1_3_2_1_28_1","volume-title":"Rtlfixer: Automatically fixing rtl syntax errors with large language models,\" arXiv preprint arXiv:2311.16543","author":"Tsai Y.","year":"2023","unstructured":"Y. Tsai, M. Liu, and H. Ren, \"Rtlfixer: Automatically fixing rtl syntax errors with large language models,\" arXiv preprint arXiv:2311.16543, 2023."},{"key":"e_1_3_2_1_29_1","volume-title":"Betterv: Controlled verilog generation with discriminative guidance,\" arXiv preprint arXiv:2402.03375","author":"Pei Z.","year":"2024","unstructured":"Z. Pei, H.-L. Zhen, M. Yuan, Y. Huang, and B. Yu, \"Betterv: Controlled verilog generation with discriminative guidance,\" arXiv preprint arXiv:2402.03375, 2024."},{"key":"e_1_3_2_1_30_1","volume-title":"A circuit domain generalization framework for efficient logic synthesis in chip design,\" arXiv preprint arXiv:2309.03208","author":"Wang Z.","year":"2023","unstructured":"Z. Wang, L. Chen, J. Wang, X. Li, Y. Bai, X. Li, M. Yuan, J. Hao, Y. Zhang, and F. Wu, \"A circuit domain generalization framework for efficient logic synthesis in chip design,\" arXiv preprint arXiv:2309.03208, 2023."},{"key":"e_1_3_2_1_31_1","volume-title":"A hierarchical adaptive multi-task reinforcement learning framework for multiplier circuit design,\" in Forty-first International Conference on Machine Learning","author":"Wang Z.","year":"2024","unstructured":"Z. Wang, J. Wang, D. Zuo, J. Yunjie, X. Xia, Y. Ma, H. Jianye, M. Yuan, Y. Zhang, and F. Wu, \"A hierarchical adaptive multi-task reinforcement learning framework for multiplier circuit design,\" in Forty-first International Conference on Machine Learning, 2024."},{"key":"e_1_3_2_1_32_1","article-title":"A unified parallel framework for lut mapping and logic optimization","author":"Liu T.","year":"2024","unstructured":"T. Liu, Y. Sun, L. Chen, X. Li, M. Yuan, and E. F. Young, \"A unified parallel framework for lut mapping and logic optimization,\" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024.","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"e_1_3_2_1_33_1","volume-title":"Logic synthesis with generative deep neural networks,\" arXiv preprint arXiv:2406.04699","author":"Li X.","year":"2024","unstructured":"X. Li, X. Li, L. Chen, X. Zhang, M. Yuan, and J. Wang, \"Logic synthesis with generative deep neural networks,\" arXiv preprint arXiv:2406.04699, 2024."},{"key":"e_1_3_2_1_34_1","volume-title":"End-to-end circuit design by predicting the next gate,\" arXiv preprint arXiv:2403.13838","author":"Li X.","year":"2024","unstructured":"X. Li, X. Li, \"Circuit transformer: End-to-end circuit design by predicting the next gate,\" arXiv preprint arXiv:2403.13838, 2024."},{"key":"e_1_3_2_1_35_1","first-page":"1","volume-title":"IEEE","author":"Liu M.","year":"2023","unstructured":"M. Liu, N. Pinckney, B. Khailany, and H. Ren, \"Verilogeval: Evaluating large language models for verilog code generation,\" in 2023 IEEE\/ACM International Conference on Computer Aided Design (ICCAD). IEEE, 2023, pp. 1--8."},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1162\/tacl_a_00638"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1145\/2939672.2939785"},{"key":"e_1_3_2_1_38_1","first-page":"824","article-title":"Chain-of-thought prompting elicits reasoning in large language models","volume":"35","author":"Wei J.","year":"2022","unstructured":"J. Wei, X. Wang, D. Schuurmans, M. Bosma, F. Xia, E. Chi, Q. V. Le, D. Zhou et al., \"Chain-of-thought prompting elicits reasoning in large language models,\" Advances in Neural Information Processing Systems, vol. 35, pp. 24 824--24 837, 2022.","journal-title":"Advances in Neural Information Processing Systems"},{"key":"e_1_3_2_1_39_1","volume-title":"Retrieval-augmented generation for large language models: A survey,\" arXiv preprint arXiv:2312.10997","author":"Gao Y.","year":"2023","unstructured":"Y. Gao, Y. Xiong, X. Gao, K. Jia, J. Pan, Y. Bi, Y. Dai, J. Sun, and H. Wang, \"Retrieval-augmented generation for large language models: A survey,\" arXiv preprint arXiv:2312.10997, 2023."},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1145\/234313.234367"},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1016\/S0306-4573(02)00021-3"},{"key":"e_1_3_2_1_42_1","first-page":"397","article-title":"Using confidence bounds for exploitation-exploration trade-offs","volume":"3","author":"Auer P.","year":"2002","unstructured":"P. Auer, \"Using confidence bounds for exploitation-exploration trade-offs,\" Journal of Machine Learning Research, vol. 3, no. Nov, pp. 397--422, 2002.","journal-title":"Journal of Machine Learning Research"},{"key":"e_1_3_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1201\/b19714"},{"key":"e_1_3_2_1_44_1","first-page":"33","article-title":"Combinational equivalence checking using satisfiability and recursive learning,\" in Proceedings of the conference on Design, automation and test","author":"Marques-Silva J.","year":"1999","unstructured":"J. Marques-Silva and T. Glass, \"Combinational equivalence checking using satisfiability and recursive learning,\" in Proceedings of the conference on Design, automation and test in Europe, 1999, pp. 33--es.","journal-title":"Europe"},{"key":"e_1_3_2_1_45_1","first-page":"169","article-title":"Equivalence checking using gr\u00f6bner bases,\" in 2016 Formal Methods in Computer-Aided Design (FMCAD)","author":"Sayed-Ahmed A.","year":"2016","unstructured":"A. Sayed-Ahmed, D. Gro\u00dfe, M. Soeken, and R. Drechsler, \"Equivalence checking using gr\u00f6bner bases,\" in 2016 Formal Methods in Computer-Aided Design (FMCAD). IEEE, 2016, pp. 169--176.","journal-title":"IEEE"},{"key":"e_1_3_2_1_46_1","first-page":"151","article-title":"Automated whitebox fuzz testing","volume":"8","author":"Godefroid P.","year":"2008","unstructured":"P. Godefroid, M. Y. Levin, D. A. Molnar et al., \"Automated whitebox fuzz testing.\" in NDSS, vol. 8, 2008, pp. 151--166.","journal-title":"NDSS"},{"key":"e_1_3_2_1_47_1","volume-title":"Aleman et al., \"Gpt-4 technical report,\" arXiv preprint arXiv:2303.08774","author":"Achiam J.","year":"2023","unstructured":"J. Achiam, S. Adler, S. Agarwal, L. Ahmad, I. Akkaya, Aleman et al., \"Gpt-4 technical report,\" arXiv preprint arXiv:2303.08774, 2023."},{"key":"e_1_3_2_1_48_1","first-page":"43","volume-title":"IEEE","author":"Coward S.","year":"2022","unstructured":"S. Coward, G. A. Constantinides, and T. Drane, \"Automatic datapath optimization using e-graphs,\" in 2022 IEEE 29th Symposium on Computer Arithmetic (ARITH). IEEE, 2022, pp. 43--50."},{"key":"e_1_3_2_1_49_1","volume-title":"Gelly et al., \"An image is worth 16x16 words: Transformers for image recognition at scale,\" arXiv preprint arXiv:2010.11929","author":"Dosovitskiy A.","year":"2020","unstructured":"A. Dosovitskiy, L. Beyer, A. Kolesnikov, D. Weissenborn, X. Zhai, T. Unterthiner, M. Dehghani, M. Minderer, G. Heigold, S. Gelly et al., \"An image is worth 16x16 words: Transformers for image recognition at scale,\" arXiv preprint arXiv:2010.11929, 2020."},{"key":"e_1_3_2_1_50_1","volume-title":"Bhosale et al., \"Llama 2: Open foundation and fine-tuned chat models,\" arXiv preprint arXiv:2307.09288","author":"Touvron H.","year":"2023","unstructured":"H. Touvron, L. Martin, K. Stone, P. Albert, A. Almahairi, Y. Babaei, N. Bashlykov, S. Batra, P. Bhargava, S. Bhosale et al., \"Llama 2: Open foundation and fine-tuned chat models,\" arXiv preprint arXiv:2307.09288, 2023."},{"key":"e_1_3_2_1_51_1","volume-title":"Dai et al., \"Deepseek llm: Scaling open-source language models with longtermism,\" arXiv preprint arXiv:2401.02954","author":"Bi X.","year":"2024","unstructured":"X. Bi, D. Chen, G. Chen, S. Chen, D. Dai et al., \"Deepseek llm: Scaling open-source language models with longtermism,\" arXiv preprint arXiv:2401.02954, 2024."},{"issue":"99","key":"e_1_3_2_1_52_1","first-page":"3","article-title":"Icarus verilog: open-source verilog more than a year later","volume":"2002","author":"Williams S.","year":"2002","unstructured":"S. Williams and M. Baxter, \"Icarus verilog: open-source verilog more than a year later,\" Linux Journal, vol. 2002, no. 99, p. 3, 2002.","journal-title":"Linux Journal"},{"key":"e_1_3_2_1_53_1","first-page":"24","volume-title":"CAV 2010, Edinburgh, UK, July 15--19, 2010. Proceedings 22","author":"Brayton R.","year":"2010","unstructured":"R. Brayton and A. Mishchenko, \"Abc: An academic industrial-strength verification tool,\" in Computer Aided Verification: 22nd International Conference, CAV 2010, Edinburgh, UK, July 15--19, 2010. Proceedings 22. Springer, 2010, pp. 24--40."}],"event":{"name":"ICCAD '24: 43rd IEEE\/ACM International Conference on Computer-Aided Design","location":"Newark Liberty International Airport Marriott New York NY USA","acronym":"ICCAD '24","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CAS","IEEE CEDA","IEEE EDS"]},"container-title":["Proceedings of the 43rd IEEE\/ACM International Conference on Computer-Aided Design"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3676536.3676775","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3676536.3676775","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T23:43:58Z","timestamp":1750290238000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3676536.3676775"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,10,27]]},"references-count":53,"alternative-id":["10.1145\/3676536.3676775","10.1145\/3676536"],"URL":"https:\/\/doi.org\/10.1145\/3676536.3676775","relation":{},"subject":[],"published":{"date-parts":[[2024,10,27]]},"assertion":[{"value":"2025-04-09","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}