{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,11]],"date-time":"2026-03-11T16:35:27Z","timestamp":1773246927811,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":48,"publisher":"ACM","license":[{"start":{"date-parts":[[2024,10,27]],"date-time":"2024-10-27T00:00:00Z","timestamp":1729987200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"funding National Natural Science Foundation of China","award":["62122021"],"award-info":[{"award-number":["62122021"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2024,10,27]]},"DOI":"10.1145\/3676536.3676801","type":"proceedings-article","created":{"date-parts":[[2025,4,9]],"date-time":"2025-04-09T13:21:20Z","timestamp":1744204880000},"page":"1-9","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":21,"title":["MEIC: Re-thinking RTL Debug Automation using LLMs"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0009-0005-8312-4782","authenticated-orcid":false,"given":"Ke","family":"Xu","sequence":"first","affiliation":[{"name":"Southeast University, Nanjing, China"}]},{"ORCID":"https:\/\/orcid.org\/0009-0005-1712-9059","authenticated-orcid":false,"given":"Jialin","family":"Sun","sequence":"additional","affiliation":[{"name":"Southeast University, Nanjing, China"}]},{"ORCID":"https:\/\/orcid.org\/0009-0001-4169-602X","authenticated-orcid":false,"given":"Yuchen","family":"Hu","sequence":"additional","affiliation":[{"name":"Southeast University, Nanjing, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3630-2249","authenticated-orcid":false,"given":"Xinwei","family":"Fang","sequence":"additional","affiliation":[{"name":"Department of computer science, University of York, York, United Kingdom"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5520-1326","authenticated-orcid":false,"given":"Weiwei","family":"Shan","sequence":"additional","affiliation":[{"name":"Southeast University, Nanjing, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1998-6733","authenticated-orcid":false,"given":"Xi","family":"Wang","sequence":"additional","affiliation":[{"name":"Southeast University, Nanjing, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8509-3167","authenticated-orcid":false,"given":"Zhe","family":"Jiang","sequence":"additional","affiliation":[{"name":"Southeast University, Nanjing, China"}]}],"member":"320","published-online":{"date-parts":[[2025,4,9]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"Fixing hardware security bugs with large language models. arXiv preprint arXiv:2302.01215","author":"Ahmad Baleegh","year":"2023","unstructured":"Baleegh Ahmad, Shailja Thakur, Benjamin Tan, Ramesh Karri, and Hammond Pearce. 2023. Fixing hardware security bugs with large language models. arXiv preprint arXiv:2302.01215 (2023)."},{"key":"e_1_3_2_1_2_1","volume-title":"MEASURING AND MITIGATING HALLUCINATIONS IN LARGE LANGUAGE MODELS: AMULTIFACETED APPROACH.","author":"Amatriain Xavier","year":"2024","unstructured":"Xavier Amatriain. 2024. MEASURING AND MITIGATING HALLUCINATIONS IN LARGE LANGUAGE MODELS: AMULTIFACETED APPROACH. (2024)."},{"key":"e_1_3_2_1_3_1","volume-title":"Chip-Chat: Challenges and Opportunities in Conversational Hardware Design. arXiv preprint arXiv:2305.13243","author":"Blocklove Jason","year":"2023","unstructured":"Jason Blocklove, Siddharth Garg, Ramesh Karri, and Hammond Pearce. 2023. Chip-Chat: Challenges and Opportunities in Conversational Hardware Design. arXiv preprint arXiv:2305.13243 (2023)."},{"key":"e_1_3_2_1_4_1","volume-title":"ChipGPT: How far are we from natural language hardware design. arXiv preprint arXiv:2305.14019","author":"Chang Kaiyan","year":"2023","unstructured":"Kaiyan Chang, Ying Wang, Haimeng Ren, Mengdi Wang, Shengwen Liang, Yinhe Han, Huawei Li, and Xiaowei Li. 2023. ChipGPT: How far are we from natural language hardware design. arXiv preprint arXiv:2305.14019 (2023)."},{"key":"e_1_3_2_1_5_1","volume-title":"Jared Kaplan, Harri Edwards, Yuri Burda, Nicholas Joseph, Greg Brockman, et al.","author":"Chen Mark","year":"2021","unstructured":"Mark Chen, Jerry Tworek, Heewoo Jun, Qiming Yuan, Henrique Ponde de Oliveira Pinto, Jared Kaplan, Harri Edwards, Yuri Burda, Nicholas Joseph, Greg Brockman, et al. 2021. Evaluating large language models trained on code. arXiv preprint arXiv:2107.03374 (2021)."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/3583780.3614905"},{"key":"e_1_3_2_1_7_1","volume-title":"Verilog: Frequently Asked Questions: Language, Applications and Extensions","author":"Chonnad Shivakumar S","year":"2007","unstructured":"Shivakumar S Chonnad and Needamangalam B Balachander. 2007. Verilog: Frequently Asked Questions: Language, Applications and Extensions. Springer Science & Business Media."},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1609\/aaai.v38i21.30364"},{"key":"e_1_3_2_1_9_1","volume-title":"Vasudev Gohil, Shailja Thakur, Ramesh Karri, Siddharth Garg, and Jeyavijayan Rajendran.","author":"DeLorenzo Matthew","year":"2024","unstructured":"Matthew DeLorenzo, Animesh Basak Chowdhury, Vasudev Gohil, Shailja Thakur, Ramesh Karri, Siddharth Garg, and Jeyavijayan Rajendran. 2024. Make Every Move Count: LLM-based High-Quality RTL Code Generation Using MCTS. arXiv preprint arXiv:2402.03289 (2024)."},{"key":"e_1_3_2_1_10_1","volume-title":"Lahiri","author":"Fakhoury Sarah","year":"2024","unstructured":"Sarah Fakhoury, Aaditya Naik, Georgios Sakkas, Saikat Chakraborty, and Shuvendu K. Lahiri. 2024. LLM-based Test-driven Interactive Code Generation: User Study and Empirical Evaluation. arXiv:2404.10100 [cs.SE]"},{"key":"e_1_3_2_1_11_1","volume-title":"AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMs. arXiv preprint arXiv:2402.00386","author":"Fang Wenji","year":"2024","unstructured":"Wenji Fang, Mengming Li, Min Li, Zhiyuan Yan, Shang Liu, Hongce Zhang, and Zhiyao Xie. 2024. AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMs. arXiv preprint arXiv:2402.00386 (2024)."},{"key":"e_1_3_2_1_12_1","volume-title":"Don't Hallucinate","author":"Feng Shangbin","year":"2024","unstructured":"Shangbin Feng, Weijia Shi, Yike Wang, Wenxuan Ding, Vidhisha Balachandran, and Yulia Tsvetkov. 2024. Don't Hallucinate, Abstain: Identifying LLM Knowledge Gaps via Multi-LLM Collaboration. arXiv preprint arXiv:2402.00367 (2024)."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/AsianHOST59942.2023.10409307"},{"key":"e_1_3_2_1_14_1","volume-title":"Truth-o-meter: Collaborating with llm in fighting its hallucinations.","author":"Galitsky Boris A","year":"2023","unstructured":"Boris A Galitsky. 2023. Truth-o-meter: Collaborating with llm in fighting its hallucinations. (2023)."},{"key":"e_1_3_2_1_15_1","volume-title":"ASIC: Hardware Implementation with Large Language Model. arXiv preprint arXiv:2403.07039","author":"Goh Emil","year":"2024","unstructured":"Emil Goh, Maoyang Xiang, I Wey, T Hui Teo, et al. 2024. From English to ASIC: Hardware Implementation with Large Language Model. arXiv preprint arXiv:2403.07039 (2024)."},{"key":"e_1_3_2_1_16_1","unstructured":"Muhammad Hassan Sallar Ahmadi-Pour Khushboo Qayyum Chandan Kumar Jha and Rolf Drechsler. [n. d.]. LLM-guided Formal Verification Coupled with Mutation Testing. ([n. d.])."},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.18653\/v1\/2023.findings-emnlp.123"},{"key":"e_1_3_2_1_18_1","unstructured":"Xue Jiang Yihong Dong Lecheng Wang Zheng Fang Qiwei Shang Ge Li Zhi Jin and Wenpin Jiao. 2023. Self-planning Code Generation with Large Language Models. arXiv:2303.06689 [cs.SE]"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2021.3075422"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/3620666.3651346"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2834439"},{"key":"e_1_3_2_1_22_1","volume-title":"Chipnemo: Domain-adapted llms for chip design. arXiv preprint arXiv:2311.00176","author":"Liu Mingjie","year":"2023","unstructured":"Mingjie Liu, Teodor-Dumitru Ene, Robert Kirby, Chris Cheng, Nathaniel Pinckney, Rongjian Liang, Jonah Alben, Himyanshu Anand, Sanmitra Banerjee, Ismet Bayraktaroglu, et al. 2023. Chipnemo: Domain-adapted llms for chip design. arXiv preprint arXiv:2311.00176 (2023)."},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD57390.2023.10323812"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1007\/s00778-022-00733-5"},{"key":"e_1_3_2_1_25_1","volume-title":"RTLLM: An open-source benchmark for design rtl generation with large language model. arXiv preprint arXiv:2308.05345","author":"Lu Yao","year":"2023","unstructured":"Yao Lu, Shang Liu, Qijun Zhang, and Zhiyao Xie. 2023. RTLLM: An open-source benchmark for design rtl generation with large language model. arXiv preprint arXiv:2308.05345 (2023)."},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/3597503.3639187"},{"key":"e_1_3_2_1_27_1","unstructured":"OpenAI. 2024. ChatGPT - Fine-Tuning. https:\/\/platform.openai.com\/docs\/guides\/fine-tuning"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1007\/s10439-023-03306-x"},{"key":"e_1_3_2_1_29_1","volume-title":"RTL Coding Guidelines. Digital VLSI Systems Design: A Design Manual for Implementation of Projects on FPGAs and ASICs Using Verilog","author":"Ramachandran S","year":"2007","unstructured":"S Ramachandran. 2007. RTL Coding Guidelines. Digital VLSI Systems Design: A Design Manual for Implementation of Projects on FPGAs and ASICs Using Verilog (2007), 187--214."},{"key":"e_1_3_2_1_30_1","volume-title":"Sriparna Saha, Vinija Jain, Samrat Mondal, and Aman Chadha.","author":"Sahoo Pranab","year":"2024","unstructured":"Pranab Sahoo, Ayush Kumar Singh, Sriparna Saha, Vinija Jain, Samrat Mondal, and Aman Chadha. 2024. A Systematic Survey of Prompt Engineering in Large Language Models: Techniques and Applications. arXiv preprint arXiv:2402.07927 (2024)."},{"key":"e_1_3_2_1_31_1","unstructured":"SEIMENS. 2024. ModelSim. https:\/\/eda.sw.siemens.com\/en-US\/ic\/modelsim\/"},{"key":"e_1_3_2_1_32_1","volume-title":"Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS). ACM. ACM Press.","author":"Srikumar Priya","year":"2023","unstructured":"Priya Srikumar. 2023. Fast and wrong: The case for formally specifying hardware with LLMS. In Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS). ACM. ACM Press."},{"key":"e_1_3_2_1_33_1","volume-title":"9th Internatioinal HDL Conference (HDLCon).","author":"Sutherland Stuart","year":"2000","unstructured":"Stuart Sutherland. 2000. The IEEE Verilog 1364--2001 Standard What's New, and Why You Need It. In 9th Internatioinal HDL Conference (HDLCon)."},{"key":"e_1_3_2_1_34_1","volume-title":"Verilog and SystemVerilog Gotchas: 101 Common Coding Errors and How to Avoid Them","author":"Sutherland Stuart","unstructured":"Stuart Sutherland and Don Mills. 2010. Verilog and SystemVerilog Gotchas: 101 Common Coding Errors and How to Avoid Them. Springer Science & Business Media."},{"key":"e_1_3_2_1_35_1","volume-title":"Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 1--6.","author":"Thakur Shailja","year":"2023","unstructured":"Shailja Thakur, Baleegh Ahmad, Zhenxing Fan, Hammond Pearce, Benjamin Tan, Ramesh Karri, Brendan Dolan-Gavitt, and Siddharth Garg. 2023. Benchmarking large language models for automated verilog rtl code generation. In 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 1--6."},{"key":"e_1_3_2_1_36_1","volume-title":"Verigen: A large language model for verilog code generation. arXiv preprint arXiv:2308.00708","author":"Thakur Shailja","year":"2023","unstructured":"Shailja Thakur, Baleegh Ahmad, Hammond Pearce, Benjamin Tan, Brendan Dolan-Gavitt, Ramesh Karri, and Siddharth Garg. 2023. Verigen: A large language model for verilog code generation. arXiv preprint arXiv:2308.00708 (2023)."},{"key":"e_1_3_2_1_37_1","volume-title":"Debugbench: Evaluating debugging capability of large language models. arXiv preprint arXiv:2401.04621","author":"Tian Runchu","year":"2024","unstructured":"Runchu Tian, Yining Ye, Yujia Qin, Xin Cong, Yankai Lin, Zhiyuan Liu, and Maosong Sun. 2024. Debugbench: Evaluating debugging capability of large language models. arXiv preprint arXiv:2401.04621 (2024)."},{"key":"e_1_3_2_1_38_1","volume-title":"RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Models. arXiv preprint arXiv:2311.16543","author":"Tsai YunDa","year":"2023","unstructured":"YunDa Tsai, Mingjie Liu, and Haoxing Ren. 2023. RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Models. arXiv preprint arXiv:2311.16543 (2023)."},{"key":"e_1_3_2_1_39_1","volume-title":"Software\/Hardware Co-design for LLM and Its Application for Design Verification. In 2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC). IEEE, 435--441","author":"Wan Lily Jiaxin","year":"2024","unstructured":"Lily Jiaxin Wan, Yingbing Huang, Yuhong Li, Hanchen Ye, Jinghua Wang, Xiaofan Zhang, and Deming Chen. 2024. Software\/Hardware Co-design for LLM and Its Application for Design Verification. In 2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC). IEEE, 435--441."},{"key":"e_1_3_2_1_40_1","volume-title":"Denny Zhou, et al.","author":"Wei Jason","year":"2022","unstructured":"Jason Wei, Xuezhi Wang, Dale Schuurmans, Maarten Bosma, Fei Xia, Ed Chi, Quoc V Le, Denny Zhou, et al. 2022. Chain-of-thought prompting elicits reasoning in large language models. Advances in neural information processing systems 35 (2022), 24824--24837."},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1145\/3489517.3530434"},{"key":"e_1_3_2_1_42_1","volume-title":"DECISIVE: Designing Critical Systems With Iterative Automated Safety Analysis","author":"Wei Ran","year":"2023","unstructured":"Ran Wei, Zhe Jiang, Xiaoran Guo, Ruizhe Yang, Haitao Mei, Athanasios Zolotas, and Tim Kelly. 2023. DECISIVE: Designing Critical Systems With Iterative Automated Safety Analysis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2023)."},{"key":"e_1_3_2_1_43_1","volume-title":"A prompt pattern catalog to enhance prompt engineering with chatgpt. arXiv preprint arXiv:2302.11382","author":"White Jules","year":"2023","unstructured":"Jules White, Quchen Fu, Sam Hays, Michael Sandborn, Carlos Olea, Henry Gilbert, Ashraf Elnashar, Jesse Spencer-Smith, and Douglas C Schmidt. 2023. A prompt pattern catalog to enhance prompt engineering with chatgpt. arXiv preprint arXiv:2302.11382 (2023)."},{"key":"e_1_3_2_1_44_1","unstructured":"Henry Wong. 2019. HDLBits - Practice FPGA Problems. https:\/\/hdlbits.01xz.net\/wiki\/Main_Page"},{"key":"e_1_3_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1145\/3491102.3517582"},{"key":"e_1_3_2_1_46_1","volume-title":"Wenyi Xiao, Mingxuan Yuan, Yu Huang, Lei Chen, and Bei Yu.","author":"Yao Xufeng","year":"2024","unstructured":"Xufeng Yao, Haoyang Li, Tsz Ho Chan, Wenyi Xiao, Mingxuan Yuan, Yu Huang, Lei Chen, and Bei Yu. 2024. HDLdebugger: Streamlining HDL debugging with Large Language Models. arXiv preprint arXiv:2403.11671 (2024)."},{"key":"e_1_3_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.1145\/3544548.3581388"},{"key":"e_1_3_2_1_48_1","unstructured":"Yue Zhang Yafu Li Leyang Cui Deng Cai Lemao Liu Tingchen Fu Xinting Huang Enbo Zhao Yu Zhang Yulong Chen et al. 2023. Siren's song in the ai ocean: A survey on hallucination in large language models. arXiv preprint arXiv:2309.01219 (2023)."}],"event":{"name":"ICCAD '24: 43rd IEEE\/ACM International Conference on Computer-Aided Design","location":"Newark Liberty International Airport Marriott New York NY USA","acronym":"ICCAD '24","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CAS","IEEE CEDA","IEEE EDS"]},"container-title":["Proceedings of the 43rd IEEE\/ACM International Conference on Computer-Aided Design"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3676536.3676801","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3676536.3676801","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T01:18:44Z","timestamp":1750295924000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3676536.3676801"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,10,27]]},"references-count":48,"alternative-id":["10.1145\/3676536.3676801","10.1145\/3676536"],"URL":"https:\/\/doi.org\/10.1145\/3676536.3676801","relation":{},"subject":[],"published":{"date-parts":[[2024,10,27]]},"assertion":[{"value":"2025-04-09","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}