{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T01:40:08Z","timestamp":1750297208983,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":21,"publisher":"ACM","license":[{"start":{"date-parts":[[2024,10,27]],"date-time":"2024-10-27T00:00:00Z","timestamp":1729987200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["No. 62234010"],"award-info":[{"award-number":["No. 62234010"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"name":"The 111 Project of China","award":["No. 61574109"],"award-info":[{"award-number":["No. 61574109"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2024,10,27]]},"DOI":"10.1145\/3676536.3676833","type":"proceedings-article","created":{"date-parts":[[2025,4,9]],"date-time":"2025-04-09T13:21:20Z","timestamp":1744204880000},"page":"1-9","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["TopoOrderPart: a Multi-level Scheduling-Driven Partitioning Framework for Processor-Based Emulation"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0009-0001-1341-3977","authenticated-orcid":false,"given":"Shunyang","family":"Bi","sequence":"first","affiliation":[{"name":"Xidian University, Xi'an, China"}]},{"ORCID":"https:\/\/orcid.org\/0009-0002-8737-228X","authenticated-orcid":false,"given":"Jing","family":"Tang","sequence":"additional","affiliation":[{"name":"Xidian University, Xi'an, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3427-5320","authenticated-orcid":false,"given":"Hailong","family":"You","sequence":"additional","affiliation":[{"name":"Xidian University, Xi'an, China"}]},{"ORCID":"https:\/\/orcid.org\/0009-0001-4732-5705","authenticated-orcid":false,"given":"Haonan","family":"Wu","sequence":"additional","affiliation":[{"name":"Xidian University, Xi'an, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6289-6680","authenticated-orcid":false,"given":"Cong","family":"Li","sequence":"additional","affiliation":[{"name":"Xidian University, Xi'an, China"}]},{"ORCID":"https:\/\/orcid.org\/0009-0003-3924-2154","authenticated-orcid":false,"given":"Richard","family":"Sun","sequence":"additional","affiliation":[{"name":"S2C Inc., Shenzhen, China"}]}],"member":"320","published-online":{"date-parts":[[2025,4,9]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"Cadence. 2024. Cadence palladium. https:\/\/www.cadence.com\/en_US\/home\/tools\/system-design-and-verification\/emulation-and-prototyping\/palladium.html."},{"key":"e_1_3_2_1_2_1","unstructured":"Mentor Graphics. 2024. Mentor veloce. https:\/\/eda.sw.siemens.com\/en-US\/ic\/veloce\/strato-hardware."},{"volume-title":"2007 50th Midwest Symposium on Circuits and Systems, 1505--1508","author":"Yazdanshenas Amir","key":"e_1_3_2_1_3_1","unstructured":"Amir Yazdanshenas and Mohammed A. S. Khalid. 2007. A new scheduling algorithm for processor-based logic emulation systems. In 2007 50th Midwest Symposium on Circuits and Systems, 1505--1508."},{"key":"e_1_3_2_1_4_1","unstructured":"Amir Ali Yazdanshenas. 2006. Hardware design and cad for processor-based logic emulation systems. In Electronic Theses and Dissertations."},{"key":"e_1_3_2_1_5_1","unstructured":"Marwan Kanaan. 2007. A low-cost processor-based logic emulation system using fpgas. In Electronic Theses and Dissertations."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD57390.2023.10323694"},{"key":"e_1_3_2_1_7_1","first-page":"216","article-title":"Processor based logic simulation acceleration and emulation system. (Mar. 2022)","volume":"17","author":"Fu Yong","year":"2022","unstructured":"Yong Fu. 2022. Processor based logic simulation acceleration and emulation system. (Mar. 2022). US Patent App. 17\/448,216.","journal-title":"US Patent App."},{"key":"e_1_3_2_1_8_1","first-page":"786","article-title":"Systems and methods for distributed and parallelized emulation processor configuration. (Jan. 2024)","volume":"11","author":"William Hung Ngai Ngai","year":"2024","unstructured":"Ngai Ngai William Hung and Amiya Ranjan Satapathy. 2024. Systems and methods for distributed and parallelized emulation processor configuration. (Jan. 2024). US Patent App. 11\/868,786.","journal-title":"US Patent App."},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/92.748202"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/71.780863"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1137\/1.9781611974317.5"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/CCGRID.2017.101"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1137\/18M1176865"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1137\/1.9781611976472.1"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/3508352.3549390"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2023.3332268"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD57390.2023.10323975"},{"key":"e_1_3_2_1_18_1","volume-title":"ALENEX'17","author":"Schlag Sebastian","year":"2017","unstructured":"Sebastian Schlag, Yaroslav Akhremtsev, Tobias Heuer, and Peter Sanders. 2017. Engineering a direct k-way hypergraph partitioning algorithm. In ALENEX'17."},{"key":"e_1_3_2_1_19_1","unstructured":"G. Karypis and V. Kumar. 1998. Hmetis a hypergraph partitioning package version 1.5.3. http:\/\/glaros.dtc.umn.edu\/gkhome\/fetch\/sw\/hMETIS\/manual.pdf."},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2013.6645503"},{"key":"e_1_3_2_1_21_1","unstructured":"2024. Dah benchmark generated from the titan23. https:\/\/drive.google.com\/file\/d\/1J6wE7AwuBvnZZfICbnqa42Kia8yXcF4d\/view?usp=drive_link."}],"event":{"name":"ICCAD '24: 43rd IEEE\/ACM International Conference on Computer-Aided Design","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CAS","IEEE CEDA","IEEE EDS"],"location":"Newark Liberty International Airport Marriott New York NY USA","acronym":"ICCAD '24"},"container-title":["Proceedings of the 43rd IEEE\/ACM International Conference on Computer-Aided Design"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3676536.3676833","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3676536.3676833","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T01:18:44Z","timestamp":1750295924000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3676536.3676833"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,10,27]]},"references-count":21,"alternative-id":["10.1145\/3676536.3676833","10.1145\/3676536"],"URL":"https:\/\/doi.org\/10.1145\/3676536.3676833","relation":{},"subject":[],"published":{"date-parts":[[2024,10,27]]},"assertion":[{"value":"2025-04-09","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}