{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,5]],"date-time":"2026-03-05T15:46:09Z","timestamp":1772725569915,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":56,"publisher":"ACM","license":[{"start":{"date-parts":[[2025,3,30]],"date-time":"2025-03-30T00:00:00Z","timestamp":1743292800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2025,3,30]]},"DOI":"10.1145\/3676641.3716020","type":"proceedings-article","created":{"date-parts":[[2025,3,27]],"date-time":"2025-03-27T16:47:32Z","timestamp":1743094052000},"page":"1060-1075","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["ShadowLoad: Injecting State into Hardware Prefetchers"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0009-0007-1201-0299","authenticated-orcid":false,"given":"Lorenz","family":"Hetterich","sequence":"first","affiliation":[{"name":"CISPA Helmholtz Center for Information Security, Saarbr\u00fccken, Saarland, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0008-8029-0621","authenticated-orcid":false,"given":"Fabian","family":"Thomas","sequence":"additional","affiliation":[{"name":"CISPA Helmholtz Center for Information Security, Saarbr\u00fccken, Saarland, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0002-6684-2035","authenticated-orcid":false,"given":"Lukas","family":"Gerlach","sequence":"additional","affiliation":[{"name":"CISPA Helmholtz Center for Information Security, Saarbr\u00fccken, Saarland, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0007-9094-6412","authenticated-orcid":false,"given":"Ruiyi","family":"Zhang","sequence":"additional","affiliation":[{"name":"CISPA Helmholtz Center for Information Security, Saarbr\u00fccken, Saarland, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0003-4550-1810","authenticated-orcid":false,"given":"Nils","family":"Bernsdorf","sequence":"additional","affiliation":[{"name":"CISPA Helmholtz Center for Information Security, Saarbr\u00fccken, Saarland, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0006-1938-2709","authenticated-orcid":false,"given":"Eduard","family":"Ebert","sequence":"additional","affiliation":[{"name":"CISPA Helmholtz Center for Information Security, Saarbr\u00fccken, Saarland, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6744-3410","authenticated-orcid":false,"given":"Michael","family":"Schwarz","sequence":"additional","affiliation":[{"name":"CISPA Helmholtz Center for Information Security, Saarbr\u00fccken, Saarland, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2025,3,30]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"2023. AMD SEV-SNP: Strengthening VM Isolation with Integrity Protection and More. https:\/\/www.amd.com\/system\/files\/TechDocs\/SEVSNP-strengthening-vm-isolation-with-integrity-protection-andmore.pdf"},{"key":"e_1_3_2_1_2_1","unstructured":"2024. AMD64 Architecture Programmer's Manual. https:\/\/www.amd.com\/content\/dam\/amd\/en\/documents\/processor-techdocs\/programmer-references\/24593.pdf"},{"key":"e_1_3_2_1_3_1","unstructured":"Daniel J. Bernstein. 2005. Cache-Timing Attacks on AES. http:\/\/cr.yp.to\/antiforgery\/cachetiming-20050414.pdf"},{"key":"e_1_3_2_1_4_1","unstructured":"Pietro Borrello Andreas Kogler Martin Schwarzl Moritz Lipp Daniel Gruss and Michael Schwarz. 2022. \u00c6PIC Leak: Architecturally Leaking Uninitialized Data from the Microarchitecture. In USENIX Security. https:\/\/www.usenix.org\/system\/files\/sec22-borrello.pdf"},{"key":"e_1_3_2_1_5_1","volume-title":"Michael Schwarz, Moritz Lipp, Benjamin von","author":"Canella Claudio","year":"2019","unstructured":"Claudio Canella, Jo Van Bulck, Michael Schwarz, Moritz Lipp, Benjamin von Berg, Philipp Ortner, Frank Piessens, Dmitry Evtyushkin, and Daniel Gruss. 2019. A Systematic Evaluation of Transient Execution Attacks and Defenses. In USENIX Security. https:\/\/www.usenix.org\/system\/files\/sec19-canella.pdf Extended classification tree and PoCs at https:\/\/transient.fail\/.."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"crossref","unstructured":"Yun Chen Lingfeng Pei and Trevor E Carlson. 2023. AfterImage: Leaking control flow data and tracking load operations via the hardware prefetcher. In ASPLOS. https:\/\/dl.acm.org\/doi\/10.1145\/3575693.3575719","DOI":"10.1145\/3575693.3575719"},{"key":"e_1_3_2_1_7_1","volume-title":"USENIX Security Symposium. https:\/\/www.usenix.org\/system\/files\/conference\/usenixsecurity17\/sec17-disselkoen.pdf","author":"Disselkoen Craig","year":"2017","unstructured":"Craig Disselkoen, David Kohlbrenner, Leo Porter, and Dean Tullsen. 2017. PrimeAbort: A Timer-Free High-Precision L3 Cache Attack using Intel TSX. In USENIX Security Symposium. https:\/\/www.usenix.org\/system\/files\/conference\/usenixsecurity17\/sec17-disselkoen.pdf"},{"key":"e_1_3_2_1_8_1","volume-title":"ECE, and Dmitry Ponomarev.","author":"Evtyushkin Dmitry","year":"2018","unstructured":"Dmitry Evtyushkin, Ryan Riley, Nael CSE Abu-Ghazaleh, ECE, and Dmitry Ponomarev. 2018. BranchScope: A New Side-Channel Attack on Directional Branch Predictor. In ASPLOS. https:\/\/dl.acm.org\/doi\/10.1145\/3173162.3173204"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"crossref","unstructured":"Lukas Gerlach Daniel Weber Ruiyi Zhang and Michael Schwarz. 2023. A Security RISC: Microarchitectural Attacks on Hardware RISCV CPUs. In S&P. https:\/\/ieeexplore.ieee.org\/document\/10179399","DOI":"10.1109\/SP46215.2023.10179399"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"crossref","unstructured":"Daniel Gruss Cl\u00e9mentine Maurice Anders Fogh Moritz Lipp and Stefan Mangard. 2016. Prefetch Side-Channel Attacks: Bypassing SMAP and Kernel ASLR. In CCS. https:\/\/dl.acm.org\/doi\/10.1145\/2976749.2978356","DOI":"10.1145\/2976749.2978356"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"crossref","unstructured":"Daniel Gruss Cl\u00e9mentine Maurice KlausWagner and Stefan Mangard. 2016. FlushFlush: A Fast and Stealthy Cache Attack. In DIMVA. https:\/\/dl.acm.org\/doi\/10.1007\/978-3-319-40667-1_14","DOI":"10.1007\/978-3-319-40667-1_14"},{"key":"e_1_3_2_1_12_1","volume-title":"Cache Template Attacks: Automating Attacks on Inclusive Last-Level Caches. In USENIX Security Symposium. https:\/\/www.usenix.org\/system\/files\/conference\/usenixsecurity15\/sec15-paper-gruss.pdf","author":"Gruss Daniel","year":"2015","unstructured":"Daniel Gruss, Raphael Spreitzer, and Stefan Mangard. 2015. Cache Template Attacks: Automating Attacks on Inclusive Last-Level Caches. In USENIX Security Symposium. https:\/\/www.usenix.org\/system\/files\/conference\/usenixsecurity15\/sec15-paper-gruss.pdf"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"crossref","unstructured":"Yanan Guo Andrew Zigerelli Youtao Zhang and Jun Yang. 2022. Adversarial prefetch: New cross-core cache side channel attacks. In S&P. https:\/\/ieeexplore.ieee.org\/document\/9833692","DOI":"10.1109\/SP46214.2022.9833692"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"crossref","unstructured":"Lorenz Hetterich and Michael Schwarz. 2022. Branch Different - Spectre Attacks on Apple Silicon. In DIMVA. https:\/\/dl.acm.org\/doi\/10.1007\/978-3-031-09484-2_7","DOI":"10.1007\/978-3-031-09484-2_7"},{"key":"e_1_3_2_1_15_1","unstructured":"Intel. 2018. Indirect Branch Restricted Speculation. https:\/\/www.in tel.com\/content\/www\/us\/en\/developer\/articles\/technical\/softwaresecurity-guidance\/technical-documentation\/indirect-branchrestricted-speculation.html"},{"key":"e_1_3_2_1_16_1","unstructured":"Intel. 2021. Microarchitectural Data Sampling. https:\/\/www.intel.com\/content\/www\/us\/en\/developer\/articles\/technical\/softwaresecurity-guidance\/technical-documentation\/intel-analysismicroarchitectural-data-sampling.html"},{"key":"e_1_3_2_1_17_1","volume-title":"Intel 64 and IA-32 Architectures Software Developer's Manual","unstructured":"Intel. 2023. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3 (3A, 3B & 3C): System Programming Guide. https:\/\/cdrdv2.intel.com\/v1\/dl\/getContent\/671447"},{"key":"e_1_3_2_1_18_1","unstructured":"Intel Corporation. 2020. Guidelines for Mitigating Timing Side Channels Against Cryptographic Implementations. https:\/\/www.intel.com\/content\/www\/us\/en\/developer\/articles\/technical\/software-security-guidance\/secure-coding\/mitigate-timingside-channel-crypto-implementation.html"},{"key":"e_1_3_2_1_19_1","volume-title":"Kasper: Scanning for Generalized Transient Execution Gadgets in the Linux Kernel. In NDSS. https:\/\/www.ndsssymposium.org\/wp-content\/uploads\/2022-221-paper.pdf","author":"Johannesmeyer Brian","year":"2022","unstructured":"Brian Johannesmeyer, Jakob Koschel, Kaveh Razavi, Herbert Bos, and Cristiano Giuffrida. 2022. Kasper: Scanning for Generalized Transient Execution Gadgets in the Linux Kernel. In NDSS. https:\/\/www.ndsssymposium.org\/wp-content\/uploads\/2022-221-paper.pdf"},{"key":"e_1_3_2_1_20_1","volume-title":"Spectre Attacks: Exploiting Speculative Execution. In S&P. https:\/\/ieeexplore.ieee.org\/document\/8835233","author":"Kocher Paul","year":"2019","unstructured":"Paul Kocher, Jann Horn, Anders Fogh, Daniel Genkin, Daniel Gruss, Werner Haas, Mike Hamburg, Moritz Lipp, Stefan Mangard, Thomas Prescher, Michael Schwarz, and Yuval Yarom. 2019. Spectre Attacks: Exploiting Speculative Execution. In S&P. https:\/\/ieeexplore.ieee.org\/document\/8835233"},{"key":"e_1_3_2_1_21_1","unstructured":"Andreas Kogler Jonas Juffinger Lukas Giner Lukas Gerlach Martin Schwarzl Michael Schwarz Daniel Gruss and Stefan Mangard. 2023. CollidePower: Leaking Inaccessible Data with Software-based Power Side Channels. In USENIX Security. https:\/\/www.usenix.org\/system\/files\/usenixsecurity23-kogler.pdf"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"crossref","unstructured":"Jakob Koschel Cristiano Giuffrida Herbert Bos and Kaveh Razavi. 2020. TagBleed: Breaking KASLR on the Isolated Kernel Address Space Using Tagged TLBs. In EuroS&P. https:\/\/ieeexplore.ieee.org\/document\/9230388","DOI":"10.1109\/EuroSP48549.2020.00027"},{"key":"e_1_3_2_1_23_1","unstructured":"Moritz Lipp Daniel Gruss and Michael Schwarz. 2022. AMD Prefetch Attacks through Power and Time. In USENIX Security. https:\/\/www.usenix.org\/system\/files\/sec22-lipp.pdf"},{"key":"e_1_3_2_1_24_1","volume-title":"ARMageddon: Cache Attacks on Mobile Devices. In USENIX Security Symposium. https:\/\/www.usenix.org\/sys tem\/files\/conference\/usenixsecurity16\/sec16_paper_lipp.pdf","author":"Lipp Moritz","year":"2016","unstructured":"Moritz Lipp, Daniel Gruss, Raphael Spreitzer, Cl\u00e9mentine Maurice, and Stefan Mangard. 2016. ARMageddon: Cache Attacks on Mobile Devices. In USENIX Security Symposium. https:\/\/www.usenix.org\/sys tem\/files\/conference\/usenixsecurity16\/sec16_paper_lipp.pdf"},{"key":"e_1_3_2_1_25_1","volume-title":"PLATYPUS: Software-based Power Side-Channel Attacks on x86. In S&P. https: \/\/ieeexplore.ieee.org\/document\/9519416","author":"Lipp Moritz","year":"2020","unstructured":"Moritz Lipp, Andreas Kogler, David Oswald, Michael Schwarz, Catherine Easdon, Claudio Canella, and Daniel Gruss. 2020. PLATYPUS: Software-based Power Side-Channel Attacks on x86. In S&P. https: \/\/ieeexplore.ieee.org\/document\/9519416"},{"key":"e_1_3_2_1_26_1","volume-title":"USENIX Security Symposium. https:\/\/www.usenix.org\/system\/files\/conference\/usenixsecurit y18\/sec18-lipp.pdf","author":"Lipp Moritz","year":"2018","unstructured":"Moritz Lipp, Michael Schwarz, Daniel Gruss, Thomas Prescher,Werner Haas, Anders Fogh, Jann Horn, Stefan Mangard, Paul Kocher, Daniel Genkin, Yuval Yarom, and Mike Hamburg. 2018. Meltdown: Reading Kernel Memory from User Space. In USENIX Security Symposium. https:\/\/www.usenix.org\/system\/files\/conference\/usenixsecurit y18\/sec18-lipp.pdf"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"crossref","unstructured":"Chen Liu Abhishek Chakraborty Nikhil Chawla and Neer Roggel. 2022. Frequency throttling side-channel attack. In CCS. https:\/\/dl.acm.org\/doi\/10.1145\/3548606.3560682","DOI":"10.1145\/3548606.3560682"},{"key":"e_1_3_2_1_28_1","volume-title":"Lee","author":"Liu Fangfei","year":"2015","unstructured":"Fangfei Liu, Yuval Yarom, Qian Ge, Gernot Heiser, and Ruby B. Lee. 2015. Last-Level Cache Side-Channel Attacks are Practical. In S&P. https:\/\/ieeexplore.ieee.org\/document\/7163050"},{"key":"e_1_3_2_1_29_1","volume-title":"Re: Linux 4.18.1. https:\/\/lkml.iu.edu\/hypermail\/linux\/kernel\/1808.2\/00177.html","author":"LKML.","year":"2018","unstructured":"LKML. 2018. Re: Linux 4.18.1. https:\/\/lkml.iu.edu\/hypermail\/linux\/kernel\/1808.2\/00177.html"},{"key":"e_1_3_2_1_30_1","unstructured":"LKML. 2018. x86\/pti updates for 4.16. http:\/\/lkml.iu.edu\/hypermail\/linux\/kernel\/1801.3\/03399.html"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"crossref","unstructured":"Dag Arne Osvik Adi Shamir and Eran Tromer. 2006. Cache Attacks and Countermeasures: the Case of AES. In CT-RSA. https:\/\/dl.acm.org\/doi\/10.1007\/11605805_1","DOI":"10.1007\/11605805_1"},{"key":"e_1_3_2_1_32_1","unstructured":"Colin Percival. 2005. Cache Missing for Fun and Profit. In BSDCan. https:\/\/papers.freebsd.org\/2005\/cperciva-cache_missing"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"crossref","unstructured":"Till Schl\u00fcter Amit Choudhari Lorenz Hetterich Leon Trampert Hamed Nemati Ahmad Ibrahim Michael Schwarz Christian Rossow and Nils Ole Tippenhauer. 2023. FetchBench: Systematic Identification and Characterization of Proprietary Prefetchers. In CCS. https:\/\/dl.acm.org\/doi\/10.1145\/3576915.3623124","DOI":"10.1145\/3576915.3623124"},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1109\/MSEC.2020.2993896"},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"crossref","unstructured":"Michael Schwarz Moritz Lipp Claudio Canella Robert Schilling Florian Kargl and Daniel Gruss. 2020. ConTExT: A Generic Approach for Mitigating Spectre. In NDSS. https:\/\/www.ndss-symposium.org\/wpcontent\/ uploads\/2020\/02\/24271-paper.pdf","DOI":"10.14722\/ndss.2020.24271"},{"key":"e_1_3_2_1_36_1","volume-title":"Julian Stecklina, Thomas Prescher, and Daniel Gruss.","author":"Schwarz Michael","year":"2019","unstructured":"Michael Schwarz, Moritz Lipp, Daniel Moghimi, Jo Van Bulck, Julian Stecklina, Thomas Prescher, and Daniel Gruss. 2019. ZombieLoad: Cross-Privilege-Boundary Data Sampling. In CCS. https:\/\/dl.acm.org \/doi\/10.1145\/3319535.3354252"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"crossref","unstructured":"Michael Schwarz Martin Schwarzl Moritz Lipp and Daniel Gruss. 2019. NetSpectre: Read Arbitrary Memory over Network. In ESORICS. https:\/\/dl.acm.org\/doi\/10.1007\/978-3-030-29959-0_14","DOI":"10.1007\/978-3-030-29959-0_14"},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"crossref","unstructured":"Martin Schwarzl Thomas Schuster Michael Schwarz and Daniel Gruss. 2021. Speculative Dereferencing of Registers: Reviving Foreshadow. In FC. https:\/\/link.springer.com\/chapter\/10.1007\/978-3-662-64322-8_15","DOI":"10.1007\/978-3-662-64322-8_15"},{"key":"e_1_3_2_1_39_1","volume-title":"Dokeun Kwon, Ji Hoon Jeong, and Junbeom Hur.","author":"Shin Youngjoo","year":"2018","unstructured":"Youngjoo Shin, Hyung Chan Kim, Dokeun Kwon, Ji Hoon Jeong, and Junbeom Hur. 2018. Unveiling Hardware-based Data Prefetcher, a Hidden Source of Information Leakage. In CCS. https:\/\/dl.acm.org\/d oi\/10.1145\/3243734.3243736"},{"key":"e_1_3_2_1_40_1","volume-title":"LazyFP: Leaking FPU Register State using Microarchitectural Side-Channels. arXiv:1806.07480","author":"Stecklina Julian","year":"2018","unstructured":"Julian Stecklina and Thomas Prescher. 2018. LazyFP: Leaking FPU Register State using Microarchitectural Side-Channels. arXiv:1806.07480 (2018). https:\/\/arxiv.org\/abs\/1806.07480"},{"key":"e_1_3_2_1_41_1","unstructured":"Ke Sun Rodrigo Branco and Kekai Hu. 2019. A New Memory Type Against Speculative Side Channel Attacks. https:\/\/github.com\/IntelSTORMteam\/Papers\/blob\/main\/2019-A_N ew_Memory_Type_Against_Speculative_Side_Channel_Attacks.pdf"},{"key":"e_1_3_2_1_42_1","volume-title":"USENIX Security Symposium. https:\/\/www.usenix.org\/system\/files\/conference \/usenixsecurity18\/sec18-van_bulck.pdf","author":"Bulck Jo Van","year":"2018","unstructured":"Jo Van Bulck, Marina Minkin, OfirWeisse, Daniel Genkin, Baris Kasikci, Frank Piessens, Mark Silberstein, Thomas F. Wenisch, Yuval Yarom, and Raoul Strackx. 2018. Foreshadow: Extracting the Keys to the Intel SGX Kingdom with Transient Out-of-Order Execution. In USENIX Security Symposium. https:\/\/www.usenix.org\/system\/files\/conference \/usenixsecurity18\/sec18-van_bulck.pdf"},{"key":"e_1_3_2_1_43_1","volume-title":"LVI: Hijacking Transient Execution through Microarchitectural Load Value Injection. In S&P. https:\/\/ieeexplore.i eee.org\/document\/9152763","author":"Bulck Jo Van","year":"2020","unstructured":"Jo Van Bulck, Daniel Moghimi, Michael Schwarz, Moritz Lipp, Marina Minkin, Daniel Genkin, Yarom Yuval, Berk Sunar, Daniel Gruss, and Frank Piessens. 2020. LVI: Hijacking Transient Execution through Microarchitectural Load Value Injection. In S&P. https:\/\/ieeexplore.i eee.org\/document\/9152763"},{"key":"e_1_3_2_1_44_1","volume-title":"RIDL: Rogue In-flight Data Load. In S&P. https:\/\/ieeexplore.ieee.org\/document\/8835281","author":"van Schaik Stephan","year":"2019","unstructured":"Stephan van Schaik, Alyssa Milburn, Sebastian \u00d6sterlund, Pietro Frigo, Giorgi Maisuradze, Kaveh Razavi, Herbert Bos, and Cristiano Giuffrida. 2019. RIDL: Rogue In-flight Data Load. In S&P. https:\/\/ieeexplore.ieee.org\/document\/8835281"},{"key":"e_1_3_2_1_45_1","volume-title":"Augury: Using data memory-dependent prefetchers to leak data at rest. In S&P. https:\/\/ieeexplore.ieee.org\/document\/9833570","author":"Sanchez Vicarte Jose Rodrigo","year":"2022","unstructured":"Jose Rodrigo Sanchez Vicarte, Michael Flanders, Riccardo Paccagnella, Grant Garrett-Grossman, Adam Morrison, Christopher W Fletcher, and David Kohlbrenner. 2022. Augury: Using data memory-dependent prefetchers to leak data at rest. In S&P. https:\/\/ieeexplore.ieee.org\/document\/9833570"},{"key":"e_1_3_2_1_46_1","unstructured":"Gregory Vish. 2018. l1tf-poc. https:\/\/github.com\/gregvish\/l1tf-poc"},{"key":"e_1_3_2_1_47_1","unstructured":"Vish Viswanathan. 2014. Disclosure of Hardware Prefetcher Control on Some Intel Processors. https:\/\/web.archive.org\/web\/20151114175224\/https:\/\/software.intel.com\/en-us\/articles\/disclosure-of-hwprefetcher-control-on-some-intel-processors"},{"key":"e_1_3_2_1_48_1","volume-title":"Edward JM Colbert, and Paul Yu","author":"Wang Daimeng","year":"2019","unstructured":"Daimeng Wang, Ajaya Neupane, Zhiyun Qian, Nael Abu-Ghazaleh, Srikanth V Krishnamurthy, Edward JM Colbert, and Paul Yu. 2019. Unveiling your keystrokes: A Cache-based Side-channel Attack on Graphics Libraries. In NDSS. https:\/\/www.ndss-symposium.org\/wpcontent\/uploads\/2019\/02\/ndss2019_05B-3_Wang_paper.pdf"},{"key":"e_1_3_2_1_49_1","volume-title":"USENIX Security Symposium. https:\/\/www.usenix.org\/system\/files\/sec22-wang-yingchen.pdf","author":"Wang Yingchen","year":"2022","unstructured":"Yingchen Wang, Riccardo Paccagnella, Elizabeth He, Hovav Shacham, Christopher W. Fletcher, and David Kohlbrenner. 2022. Hertzbleed: Turning Power Side-Channel Attacks Into Remote Timing Attacks on x86. In USENIX Security Symposium. https:\/\/www.usenix.org\/system\/files\/sec22-wang-yingchen.pdf"},{"key":"e_1_3_2_1_50_1","volume-title":"Marina Minkin, Daniel Genkin, Baris Kasikci, Frank Piessens, Mark Silberstein, Raoul Strackx, Thomas F Wenisch, and Yuval Yarom.","year":"2018","unstructured":"OfirWeisse, Jo Van Bulck, Marina Minkin, Daniel Genkin, Baris Kasikci, Frank Piessens, Mark Silberstein, Raoul Strackx, Thomas F Wenisch, and Yuval Yarom. 2018. Foreshadow-NG: Breaking the Virtual Memory Abstraction with Transient Out-of-Order Execution. https:\/\/foreshadowattack.eu\/foreshadow-NG.pdf"},{"key":"e_1_3_2_1_51_1","volume-title":"Herbert Bos, and Cristiano Giuffrida.","author":"Wiebing Sander","year":"2024","unstructured":"Sander Wiebing, Alvise de Faveri Tron, Herbert Bos, and Cristiano Giuffrida. 2024. InSpectre Gadget: Inspecting the residual attack surface of cross-privilege Spectre v2. In USENIX Security. https:\/\/www.usenix.org\/system\/files\/usenixsecurity24-wiebing.pdf"},{"key":"e_1_3_2_1_52_1","volume-title":"SPEECHMINER: A Framework for Investigating and Measuring Speculative Execution Vulnerabilities. In NDSS. https:\/\/www.ndss-symposium.or g\/wp-content\/uploads\/2020\/02\/23105-paper.pdf","author":"Xiao Yuan","year":"2020","unstructured":"Yuan Xiao, Yinqian Zhang, and Radu Teodorescu. 2020. SPEECHMINER: A Framework for Investigating and Measuring Speculative Execution Vulnerabilities. In NDSS. https:\/\/www.ndss-symposium.or g\/wp-content\/uploads\/2020\/02\/23105-paper.pdf"},{"key":"e_1_3_2_1_53_1","volume-title":"USENIX Security Symposium. https:\/\/www.usenix.org\/system\/files\/conference\/usenixsecurity14\/sec14-paper-yarom.pdf","author":"Yarom Yuval","year":"2014","unstructured":"Yuval Yarom and Katrina Falkner. 2014. FlushReload: a High Resolution, Low Noise, L3 Cache Side-Channel Attack. In USENIX Security Symposium. https:\/\/www.usenix.org\/system\/files\/conference\/usenixsecurity14\/sec14-paper-yarom.pdf"},{"key":"e_1_3_2_1_54_1","volume-title":"CacheBleed: A Timing Attack on OpenSSL Constant Time RSA. JCEN","author":"Yarom Yuval","year":"2017","unstructured":"Yuval Yarom, Daniel Genkin, and Nadia Heninger. 2017. CacheBleed: A Timing Attack on OpenSSL Constant Time RSA. JCEN (2017). https:\/\/link.springer.com\/chapter\/10.1007\/978-3-662-53140-2_17"},{"key":"e_1_3_2_1_55_1","unstructured":"Ruiyi Zhang Taehyun Kim Daniel Weber and Michael Schwarz. 2023. WAIT for It: Bridging the Gap between Microarchitectural and Architectural Side Channels. In USENIX Security. https:\/\/www.usenix.org\/system\/files\/usenixsecurity23-zhang-ruiyi.pdf"},{"key":"e_1_3_2_1_56_1","volume-title":"BunnyHop: Exploiting the Instruction Prefetcher. In USENIX Security Symposium. https:\/\/www.usenix.org\/system\/files\/usenixsecurity23-zhangzhiyuan-bunnyhop.pdf","author":"Zhang Zhiyuan","year":"2023","unstructured":"Zhiyuan Zhang, Mingtian Tao, Sioli O'Connell, Chitchanok Chuengsatiansup, Daniel Genkin, and Yuval Yarom. 2023. BunnyHop: Exploiting the Instruction Prefetcher. In USENIX Security Symposium. https:\/\/www.usenix.org\/system\/files\/usenixsecurity23-zhangzhiyuan-bunnyhop.pdf"}],"event":{"name":"ASPLOS '25: 30th ACM International Conference on Architectural Support for Programming Languages and Operating Systems","location":"Rotterdam Netherlands","acronym":"ASPLOS '25","sponsor":["SIGPLAN ACM Special Interest Group on Programming Languages","SIGOPS ACM Special Interest Group on Operating Systems","SIGARCH ACM Special Interest Group on Computer Architecture"]},"container-title":["Proceedings of the 30th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 2"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3676641.3716020","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3676641.3716020","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,21]],"date-time":"2025-08-21T11:12:16Z","timestamp":1755774736000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3676641.3716020"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,3,30]]},"references-count":56,"alternative-id":["10.1145\/3676641.3716020","10.1145\/3676641"],"URL":"https:\/\/doi.org\/10.1145\/3676641.3716020","relation":{},"subject":[],"published":{"date-parts":[[2025,3,30]]},"assertion":[{"value":"2025-03-30","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}