{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,11]],"date-time":"2026-03-11T01:44:34Z","timestamp":1773193474501,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":92,"publisher":"ACM","license":[{"start":{"date-parts":[[2025,3,30]],"date-time":"2025-03-30T00:00:00Z","timestamp":1743292800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100006374","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["62032001"],"award-info":[{"award-number":["62032001"]}],"id":[{"id":"10.13039\/501100006374","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Beijing Natural Science Foundation","award":["L243001"],"award-info":[{"award-number":["L243001"]}]},{"name":"111 Project","award":["B18001"],"award-info":[{"award-number":["B18001"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2025,3,30]]},"DOI":"10.1145\/3676641.3716244","type":"proceedings-article","created":{"date-parts":[[2025,3,27]],"date-time":"2025-03-27T16:47:32Z","timestamp":1743094052000},"page":"192-209","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":6,"title":["C\n            <scp>T<\/scp>\n            X\n            <scp>N<\/scp>\n            L: A Software-Hardware Co-designed Solution for Efficient CXL-Based Transaction Processing"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0009-0009-8603-3850","authenticated-orcid":false,"given":"Zhao","family":"Wang","sequence":"first","affiliation":[{"name":"Peking University, School of Integrated Circuits, Beijing, China and Peking University, School of Computer Science, Beijing, China"}]},{"ORCID":"https:\/\/orcid.org\/0009-0001-5896-4799","authenticated-orcid":false,"given":"Yiqi","family":"Chen","sequence":"additional","affiliation":[{"name":"Peking University, School of Integrated Circuits, Beijing, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7760-3254","authenticated-orcid":false,"given":"Cong","family":"Li","sequence":"additional","affiliation":[{"name":"Peking University, School of Integrated Circuits, Beijing, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8854-2132","authenticated-orcid":false,"given":"Yijin","family":"Guan","sequence":"additional","affiliation":[{"name":"Alibaba Group, DAMO Academy, Hangzhou, China and Hupan Lab, Hangzhou, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8440-3875","authenticated-orcid":false,"given":"Dimin","family":"Niu","sequence":"additional","affiliation":[{"name":"Alibaba Group, DAMO Academy, Hangzhou, China and Hupan Lab, Hangzhou, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0081-8158","authenticated-orcid":false,"given":"Tianchan","family":"Guan","sequence":"additional","affiliation":[{"name":"Alibaba Group, DAMO Academy, Hangzhou, China and Hupan Lab, Hangzhou, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1431-898X","authenticated-orcid":false,"given":"Zhaoyang","family":"Du","sequence":"additional","affiliation":[{"name":"Alibaba Group, DAMO Academy, Hangzhou, China and Hupan Lab, Hangzhou, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4983-6047","authenticated-orcid":false,"given":"Xingda","family":"Wei","sequence":"additional","affiliation":[{"name":"Shanghai Jiao Tong University, Institute of Parallel and Distributed Systems, SEIEE, Shanghai, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7315-6589","authenticated-orcid":false,"given":"Guangyu","family":"Sun","sequence":"additional","affiliation":[{"name":"Peking University, School of Integrated Circuits, Beijing, China and Beijing Advanced Innovation Center for Integrated Circuits, Beijing, China"}]}],"member":"320","published-online":{"date-parts":[[2025,3,30]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/325164.325100"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/3533737"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS48437.2020.00031"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2016.7783729"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00031"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/2613908.2613912"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/99163.99182"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/356842.356846"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.14778\/3236187.3236209"},{"key":"e_1_3_2_1_10_1","volume-title":"Sniper: Exploring the Level of Abstraction for Scalable and Accurate Parallel Multi-CoreSimulation.InSC11(Seattle,Washington),ScottA","author":"Carlson Trevor E.","year":"2011","unstructured":"Trevor E. Carlson, Wim Heirman, and Lieven Eeckhout. 2011. Sniper: Exploring the Level of Abstraction for Scalable and Accurate Parallel Multi-CoreSimulation.InSC11(Seattle,Washington),ScottA.Lathrop, Jim Costa, and William Kramer (Eds.). Article 52, 12 pages."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.14778\/3007263.3007277"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2011.21"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/1807128.1807152"},{"key":"e_1_3_2_1_14_1","volume-title":"Intel\u00ae fpga compute express link (cxl) ip. https:\/\/www.intel.com\/content\/www\/us\/en\/products\/details\/fpga\/ intellectual-property\/interface-protocols\/cxl-ip.html","author":"Intel Corporation","year":"2024","unstructured":"Intel Corporation. [n.d.]. Intel\u00ae fpga compute express link (cxl) ip. https:\/\/www.intel.com\/content\/www\/us\/en\/products\/details\/fpga\/ intellectual-property\/interface-protocols\/cxl-ip.html. 2024."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/3448016.3457551"},{"key":"e_1_3_2_1_16_1","unstructured":"CXL Consortium. 2024. Compute Express Link Specification Revision 3.0. https:\/\/www.computeexpresslink.org\/download-the-specification"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/2463676.2463710"},{"key":"e_1_3_2_1_18_1","volume-title":"Proceedings of the 11th USENIX Symposium on Networked Systems Design and Imple mentation, NSDI 2014","author":"Dragojevic Aleksandar","year":"2014","unstructured":"Aleksandar Dragojevic, Dushyanth Narayanan, Miguel Castro, and Orion Hodson. 2014. FaRM: Fast Remote Memory. In Proceedings of the 11th USENIX Symposium on Networked Systems Design and Imple mentation, NSDI 2014, Seattle, WA, USA, April 2--4, 2014, Ratul Mahajan and Ion Stoica (Eds.). USENIX Association, 401--414. https:\/\/www. usenix.org\/conference\/nsdi14\/technical-sessions\/dragojevi%C4%87"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/2815400.2815425"},{"key":"e_1_3_2_1_20_1","volume-title":"Kirk Webb, Aditya Akella, Kuangching Wang, Glenn Ricart, Larry Landweber, Chip Elliott, Michael Zink, Emmanuel Cecchet, Snigdhaswin Kar, and Prabodh Mishra.","author":"Duplyakin Dmitry","year":"2019","unstructured":"Dmitry Duplyakin, Robert Ricci, Aleksander Maricq, Gary Wong, Jonathon Duerig, Eric Eide, Leigh Stoller, Mike Hibler, David John son, Kirk Webb, Aditya Akella, Kuangching Wang, Glenn Ricart, Larry Landweber, Chip Elliott, Michael Zink, Emmanuel Cecchet, Snigdhaswin Kar, and Prabodh Mishra. 2019. The Design and Opera tion of CloudLab.InProceedingsoftheUSENIXAnnualTechnicalConfer ence (ATC). 1--14. https:\/\/www.flux.utah.edu\/paper\/duplyakin-atc19"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/3613424.3623784"},{"key":"e_1_3_2_1_22_1","unstructured":"Donghyun Gouk Sangwon Lee Miryeong Kwon and Myoungsoo Jung. 2022. Direct Access High-Performance Memory Disaggregation withDirectCXL.InUSENIXATC2022 JiriSchindlerandNoaZilberman (Eds.). https:\/\/www.usenix.org\/conference\/atc22\/presentation\/gouk"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/3503222.3507762"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2004.1310767"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.14778\/3055540.3055548"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/3477132.3483566"},{"key":"e_1_3_2_1_27_1","volume-title":"Patterson","author":"Hennessy John L.","year":"2012","unstructured":"John L. Hennessy and David A. Patterson. 2012. Computer Architecture- A Quantitative Approach, 5th Edition. Morgan Kaufmann.","edition":"5"},{"key":"e_1_3_2_1_28_1","unstructured":"Intel. 2024. https:\/\/www.intel.com\/content\/www\/us\/en\/io\/quickpath technology\/quick-path-interconnect-introduction-paper.html"},{"key":"e_1_3_2_1_29_1","unstructured":"Intel. 2024. CXL Protocol Hard IP Functionality Accelerates a Wide Range of Data-Centric Workloads. https:\/\/www.intel.com\/content\/ www\/us\/en\/products\/details\/fpga\/intellectual-property\/interface protocols\/cxl-ip.html#tab-blade-1-0"},{"key":"e_1_3_2_1_30_1","unstructured":"Intel. 2024. Directory Structure in Skylake Server CPUs. https: \/\/community.intel.com\/t5\/Software-Tuning-Performance\/Directory Structure-in-Skylake-Server-CPUs\/m-p\/1185376"},{"key":"e_1_3_2_1_31_1","unstructured":"Intel. 2024. Intel\u00ae Data Direct I\/O Technology. https:\/\/www.intel. com\/content\/www\/us\/en\/io\/data-direct-i-o-technology.html"},{"key":"e_1_3_2_1_32_1","unstructured":"Intel. 2024. Intel\u00ae Memory Latency Checker v3.11b. https: \/\/www.intel.com\/content\/www\/us\/en\/developer\/articles\/tool\/intelr memory-latency-checker.html"},{"key":"e_1_3_2_1_33_1","volume-title":"CXL-ANNS: Software HardwareCollaborative Memory Disaggregation and Computation for Billion-Scale Approximate Nearest Neighbor Search. In 2023 USENIX Annual Technical Conference, USENIX ATC 2023","author":"Jang Junhyeok","year":"2023","unstructured":"Junhyeok Jang, Hanjin Choi, Hanyeoreum Bae, Seungjun Lee, Miryeong Kwon, and Myoungsoo Jung. 2023. CXL-ANNS: Software HardwareCollaborative Memory Disaggregation and Computation for Billion-Scale Approximate Nearest Neighbor Search. In 2023 USENIX Annual Technical Conference, USENIX ATC 2023, Boston, MA, USA, July 10--12, 2023, Julia Lawall and Dan Williams (Eds.). USENIX Association, 585--600. https:\/\/www.usenix.org\/conference\/atc23\/presentation\/jang"},{"key":"e_1_3_2_1_34_1","volume-title":"Proceedings of the 11th USENIX Symposium on Networked Systems Design and Implementation, NSDI 2014","author":"Jeong Eunyoung","year":"2014","unstructured":"Eunyoung Jeong, Shinae Woo, Muhammad Asim Jamshed, Haewon Jeong, SunghwanIhm,DongsuHan,andKyoungSooPark.2014. mTCP: a Highly Scalable User-level TCP Stack for Multicore Systems. In Proceedings of the 11th USENIX Symposium on Networked Systems Design and Implementation, NSDI 2014, Seattle, WA, USA, April 2--4, 2014, Ratul Mahajan and Ion Stoica (Eds.). USENIX Association, 489 502. https:\/\/www.usenix.org\/conference\/nsdi14\/technical-sessions\/ presentation\/jeong"},{"key":"e_1_3_2_1_35_1","volume-title":"Scalable and Simple Distributed Transactions with Two-Sided (RDMA) Datagram RPCs. In 12th USENIX Symposium on Operating Systems Design and Implementation, OSDI 2016","author":"Kalia Anuj","year":"2016","unstructured":"Anuj Kalia and David G. Andersen. 2016. FaSST: Fast, Scalable and Simple Distributed Transactions with Two-Sided (RDMA) Datagram RPCs. In 12th USENIX Symposium on Operating Systems Design and Implementation, OSDI 2016, Savannah, GA, USA, November 2--4, 2016, KimberlyKeetonandTimothyRoscoe(Eds.).USENIXAssociation,185 201. https:\/\/www.usenix.org\/conference\/osdi16\/technical-sessions\/ presentation\/kalia"},{"key":"e_1_3_2_1_36_1","volume-title":"Design Guidelines for High Performance RDMA Systems. In 2016 USENIX Annual Technical Conference, USENIX ATC 2016","author":"Kalia Anuj","year":"2016","unstructured":"Anuj Kalia, Michael Kaminsky, and David G. Andersen. 2016. Design Guidelines for High Performance RDMA Systems. In 2016 USENIX Annual Technical Conference, USENIX ATC 2016, Denver, CO, USA, June 22--24, 2016, Ajay GulatiandHakimWeatherspoon(Eds.).USENIXAsso ciation, 437--450. https:\/\/www.usenix.org\/conference\/atc16\/technical sessions\/presentation\/kalia"},{"key":"e_1_3_2_1_37_1","volume-title":"Tread Marks: Distributed Shared Memory on Standard Workstations and Operating Systems. In USENIX","author":"Keleher Peter","year":"1994","unstructured":"Peter Keleher, Alan L. Cox, Sandhya Dwarkadas, and Willy Zwaenepoel. 1994. Tread Marks: Distributed Shared Memory on Standard Workstations and Operating Systems. In USENIX Winter 1994 Technical Conference (USENIX Winter 1994 Tech nical Conference). USENIX Association, San Francisco, CA. https:\/\/www.usenix.org\/conference\/usenix-winter-1994-technical conference\/tread-marks-distributed-shared-memory-standard"},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1145\/139669.139676"},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1145\/3477132.3483565"},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2023.3240774"},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1145\/319566.319567"},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1979.1675439"},{"key":"e_1_3_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2024.3358861"},{"key":"e_1_3_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1145\/3575693.3578835"},{"key":"e_1_3_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1145\/2541940.2541952"},{"key":"e_1_3_2_1_46_1","doi-asserted-by":"publisher","DOI":"10.1145\/3341302.3342079"},{"key":"e_1_3_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.1145\/3470496.3527427"},{"key":"e_1_3_2_1_48_1","volume-title":"The SNOW Theorem and Latency-Optimal Read-Only Transactions. In 12th USENIX Symposium on Operating Systems Design and Implementation, OSDI 2016","author":"Lu Haonan","year":"2016","unstructured":"Haonan Lu, Christopher Hodsdon, Khiem Ngo, Shuai Mu, and Wyatt Lloyd. 2016. The SNOW Theorem and Latency-Optimal Read-Only Transactions. In 12th USENIX Symposium on Operating Systems Design and Implementation, OSDI 2016, Savannah, GA, USA, November 2--4, 2016, Kimberly Keeton and Timothy Roscoe (Eds.). USENIX Associa tion, 135--150. https:\/\/www.usenix.org\/conference\/osdi16\/technical sessions\/presentation\/lu"},{"key":"e_1_3_2_1_49_1","volume-title":"Performance Optimal Read-Only Transactions. In 14th USENIX Symposium on Operating Systems Design and Implementation, OSDI 2020","author":"Lu Haonan","year":"2020","unstructured":"Haonan Lu, Siddhartha Sen, and Wyatt Lloyd. 2020. Performance Optimal Read-Only Transactions. In 14th USENIX Symposium on Operating Systems Design and Implementation, OSDI 2020, Virtual Event, November 4--6, 2020. USENIX Association, 333--349. https: \/\/www.usenix.org\/conference\/osdi20\/presentation\/lu"},{"key":"e_1_3_2_1_50_1","doi-asserted-by":"publisher","DOI":"10.1145\/2933349.2933358"},{"key":"e_1_3_2_1_51_1","volume-title":"HydraRPC: RPC in the CXL Era. In 2024 USENIX Annual Technical Conference, USENIX ATC","author":"Ma Teng","year":"2024","unstructured":"Teng Ma, Zheng Liu, Chengkun Wei, Jialiang Huang, Youwei Zhuo, Haoyu Li, Ning Zhang, Yijin Guan, Dimin Niu, Mingxing Zhang, and Tao Ma. 2024. HydraRPC: RPC in the CXL Era. In 2024 USENIX Annual Technical Conference, USENIX ATC 2019. USENIX Association. https: \/\/www.usenix.org\/conference\/atc24\/presentation\/ma"},{"key":"e_1_3_2_1_52_1","doi-asserted-by":"publisher","DOI":"10.1145\/2168836.2168855"},{"key":"e_1_3_2_1_53_1","unstructured":"Luc Maranget Susmit Sarkar and Peter Sewell. 2012. A Tutorial In troduction to the ARM and POWER Relaxed Memory Models. https: \/\/www.cl.cam.ac.uk\/~pes20\/ppc-supplemental\/test7.pdf"},{"key":"e_1_3_2_1_54_1","doi-asserted-by":"publisher","DOI":"10.1145\/3582016.3582063"},{"key":"e_1_3_2_1_55_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2006.1598134"},{"key":"e_1_3_2_1_56_1","volume-title":"A Primer on Memory Consistency and Cache Coherence","author":"Nagarajan Vijay","unstructured":"Vijay Nagarajan, Daniel J. Sorin, Mark D. Hill, David A. Wood, and Natalie Enright Jerger. 2020. A Primer on Memory Consistency and Cache Coherence (2nd ed.). Morgan & Claypool Publishers.","edition":"2"},{"key":"e_1_3_2_1_57_1","volume-title":"USENIX ATC '15","author":"Nelson Jacob","year":"2015","unstructured":"Jacob Nelson, Brandon Holt, Brandon Myers, Preston Briggs, Luis Ceze, Simon Kahan, and Mark Oskin. 2015. Latency-Tolerant Software Distributed Shared Memory. In 2015 USENIX Annual Technical Confer ence, USENIX ATC '15, July 8--10, Santa Clara, CA, USA, Shan Lu and Erik Riedel (Eds.). USENIX Association, 291--305. https:\/\/www.usenix. org\/conference\/atc15\/technical-session\/presentation\/nelson"},{"key":"e_1_3_2_1_58_1","doi-asserted-by":"publisher","DOI":"10.1007\/3--540--44676--1_10"},{"key":"e_1_3_2_1_59_1","unstructured":"PMem.io. 2024. Persistent Memory Development Kit (PMDK). https: \/\/pmem.io\/pmdk\/."},{"key":"e_1_3_2_1_60_1","volume-title":"Irene Zhang, Samuel Madden, and Barbara Liskov.","author":"Ports Dan R. K.","year":"2010","unstructured":"Dan R. K. Ports, Austin T. Clements, Irene Zhang, Samuel Madden, and Barbara Liskov. 2010. Transactional Consistency and Automatic Management in an Application Data Cache. In 9th USENIX Symposium on Operating Systems Design and Implementation, OSDI 2010, October 4 6, 2010, Vancouver, BC, Canada, Proceedings, Remzi H. Arpaci-Dusseau and Brad Chen (Eds.). USENIX Association, 279--292. http:\/\/www. usenix.org\/events\/osdi10\/tech\/full_papers\/Ports.pdf"},{"key":"e_1_3_2_1_61_1","volume-title":"Caracal: Contention Management with Deterministic Concurrency Control. In SOSP'21: ACMSIGOPS28thSymposiumonOperatingSystemsPrinciples, Virtual Event \/ Koblenz, Germany, October 26--29","author":"Qin Dai","year":"2021","unstructured":"Dai Qin, Angela Demke Brown, and Ashvin Goel. 2021. Caracal: Contention Management with Deterministic Concurrency Control. In SOSP'21: ACMSIGOPS28thSymposiumonOperatingSystemsPrinciples, Virtual Event \/ Koblenz, Germany, October 26--29, 2021, Robbert van Renesse and Nickolai Zeldovich (Eds.). ACM, 180--194. doi:10.1145\/ 3477132.3483591"},{"key":"e_1_3_2_1_62_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.54"},{"key":"e_1_3_2_1_63_1","doi-asserted-by":"publisher","DOI":"10.1145\/1993498.1993520"},{"key":"e_1_3_2_1_64_1","volume-title":"Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems","volume":"1","author":"Schuh Henry N.","unstructured":"Henry N. Schuh, Arvind Krishnamurthy, David Culler, Henry M. Levy, Luigi Rizzo, Samira Khan, and Brent E. Stephens. 2024. CC-NIC: a Cache-Coherent Interface to the NIC. In Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 1 (ASPLOS '24). Association for Computing Machinery, New York, NY, USA, 52--68. doi:10.1145\/ 3617232.3624868"},{"key":"e_1_3_2_1_65_1","doi-asserted-by":"publisher","DOI":"10.1145\/3477132.3483555"},{"key":"e_1_3_2_1_66_1","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750379"},{"key":"e_1_3_2_1_67_1","volume-title":"Distributed OS for Hardware Resource Dis aggregation. In 2019 USENIX Annual Technical Conference, USENIX ATC","author":"Shan Yizhou","year":"2019","unstructured":"Yizhou Shan, Yutong Huang, Yilun Chen, and Yiying Zhang. 2019. LegoOS: A Disseminated, Distributed OS for Hardware Resource Dis aggregation. In 2019 USENIX Annual Technical Conference, USENIX ATC 2019, Renton, WA, USA, July 10--12, 2019, Dahlia Malkhi and Dan Tsafrir (Eds.). USENIX Association. https:\/\/www.usenix.org\/ conference\/atc19\/presentation\/shan"},{"key":"e_1_3_2_1_68_1","doi-asserted-by":"publisher","DOI":"10.1109\/HOTI55740.2022"},{"key":"e_1_3_2_1_69_1","volume-title":"Berger","author":"Sharma Debendra Das","year":"2024","unstructured":"Debendra Das Sharma, Robert Blankenship, and Daniel S. Berger. 2024. An Introduction to the Compute Express Link (CXL) Interconnect. arXiv:2306.11227 [cs.AR]"},{"key":"e_1_3_2_1_70_1","volume-title":"Scott","author":"Shriraman Arrvindh","year":"2008","unstructured":"Arrvindh Shriraman, Sandhya Dwarkadas, and Michael L. Scott. 2008. Flexible Decoupled Transactional Memory Support. In 35th Interna tional Symposium on Computer Architecture (ISCA 2008), June 21--25, 2008, Beijing, China. IEEE Computer Society, 139--150. doi:10.1109\/ ISCA.2008.17"},{"key":"e_1_3_2_1_71_1","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250676"},{"key":"e_1_3_2_1_72_1","doi-asserted-by":"publisher","DOI":"10.1145\/3373376.3378493"},{"key":"e_1_3_2_1_73_1","volume-title":"Demystifying CXL Memory with Genuine CXL-Ready Systems and Devices. CoRR abs\/2303.15375","author":"Sun Yan","year":"2023","unstructured":"Yan Sun, Yifan Yuan, Zeduo Yu, Reese Kuper, Ipoom Jeong, Ren Wang, and Nam Sung Kim. 2023. Demystifying CXL Memory with Genuine CXL-Ready Systems and Devices. CoRR abs\/2303.15375 (2023). doi:10. 48550\/arXiv.2303.15375 arXiv:2303.15375"},{"key":"e_1_3_2_1_74_1","doi-asserted-by":"publisher","DOI":"10.1145\/2213836.2213838"},{"key":"e_1_3_2_1_75_1","unstructured":"TPC-C. 2024. TPC benchmark C. https:\/\/www.tpc.org\/tpcc\/"},{"key":"e_1_3_2_1_76_1","doi-asserted-by":"publisher","DOI":"10.1145\/2517349.2522713"},{"key":"e_1_3_2_1_77_1","unstructured":"VoltDB. 2024. VoltDB. https:\/\/www.voltdb.com\/"},{"key":"e_1_3_2_1_78_1","volume-title":"andJinyang Li","author":"Wang Jiachen","year":"2021","unstructured":"Jiachen Wang, Ding Ding, Huan Wang, Conrad Christensen, Zhaoguo Wang, Haibo Chen, andJinyang Li. 2021. Polyjuice: High-Performance Transactions via Learned Concurrency Control. In 15th USENIX Sym posium on Operating Systems Design and Implementation (OSDI 21). USENIX Association, 198--216. https:\/\/www.usenix.org\/conference\/ osdi21\/presentation\/wang-jiachen"},{"key":"e_1_3_2_1_79_1","doi-asserted-by":"publisher","DOI":"10.1109\/PACT"},{"key":"e_1_3_2_1_80_1","doi-asserted-by":"publisher","DOI":"10.1145\/3468520"},{"key":"e_1_3_2_1_81_1","volume-title":"13th USENIX Symposium on Operating Systems Design and Imple mentation, OSDI 2018","author":"Wei Xingda","year":"2018","unstructured":"Xingda Wei, ZhiyuanDong,RongChen,andHaiboChen.2018. Decon structing RDMA-enabled Distributed Transactions: Hybrid is Better!. In 13th USENIX Symposium on Operating Systems Design and Imple mentation, OSDI 2018, Carlsbad, CA, USA, October 8--10, 2018, Andrea C. Arpaci-Dusseau and Geoff Voelker (Eds.). USENIX Association, 233 251. https:\/\/www.usenix.org\/conference\/osdi18\/presentation\/wei"},{"key":"e_1_3_2_1_82_1","doi-asserted-by":"publisher","DOI":"10.1145\/2815400.2815419"},{"key":"e_1_3_2_1_83_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2021.3067713"},{"key":"e_1_3_2_1_84_1","doi-asserted-by":"publisher","DOI":"10.14778\/3425879.3425889"},{"key":"e_1_3_2_1_85_1","unstructured":"Xilinx. 2024. Hash Crypto Engine. https:\/\/www.xilinx.com\/products\/ intellectual-property\/1--1pho740.html"},{"key":"e_1_3_2_1_86_1","doi-asserted-by":"publisher","DOI":"10.1109\/SP.2019.00004"},{"key":"e_1_3_2_1_87_1","doi-asserted-by":"publisher","DOI":"10.14778\/2735508.2735511"},{"key":"e_1_3_2_1_88_1","doi-asserted-by":"publisher","DOI":"10.14778\/3055330.3055335"},{"key":"e_1_3_2_1_89_1","doi-asserted-by":"publisher","DOI":"10.1145\/3600006.3613135"},{"key":"e_1_3_2_1_90_1","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2017.29"},{"key":"e_1_3_2_1_91_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00021"},{"key":"e_1_3_2_1_92_1","volume-title":"Peng Cheng, Lei Qu, Yongqiang Xiong, and Guangyu Sun.","author":"Zhou Zhe","year":"2024","unstructured":"Zhe Zhou, Yiqi Chen, Tao Zhang, Yang Wang, Ran Shu, Shuo tao Xu, Peng Cheng, Lei Qu, Yongqiang Xiong, and Guangyu Sun. 2024. Toward CXL-Native Memory Tiering via Device-Side Profiling. arXiv:2403.18702 [cs.AR"}],"event":{"name":"ASPLOS '25: 30th ACM International Conference on Architectural Support for Programming Languages and Operating Systems","location":"Rotterdam Netherlands","acronym":"ASPLOS '25","sponsor":["SIGPLAN ACM Special Interest Group on Programming Languages","SIGOPS ACM Special Interest Group on Operating Systems","SIGARCH ACM Special Interest Group on Computer Architecture"]},"container-title":["Proceedings of the 30th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 2"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3676641.3716244","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3676641.3716244","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,21]],"date-time":"2025-08-21T11:08:52Z","timestamp":1755774532000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3676641.3716244"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,3,30]]},"references-count":92,"alternative-id":["10.1145\/3676641.3716244","10.1145\/3676641"],"URL":"https:\/\/doi.org\/10.1145\/3676641.3716244","relation":{},"subject":[],"published":{"date-parts":[[2025,3,30]]},"assertion":[{"value":"2025-03-30","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}