{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:59:46Z","timestamp":1750309186762,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":63,"publisher":"ACM","license":[{"start":{"date-parts":[[2024,9,9]],"date-time":"2024-09-09T00:00:00Z","timestamp":1725840000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"name":"PHC Polonium","award":["BPN\/BFR\/2023\/1\/00045"],"award-info":[{"award-number":["BPN\/BFR\/2023\/1\/00045"]}]},{"name":"PHC Aurora","award":["49710YH"],"award-info":[{"award-number":["49710YH"]}]},{"name":"NCBR Poland and FNR Luxembourg","award":["POLLUX-XI\/14\/SpaceVote\/2023"],"award-info":[{"award-number":["POLLUX-XI\/14\/SpaceVote\/2023"]}]},{"name":"Minciencias","award":["BPIN 2021000100160"],"award-info":[{"award-number":["BPIN 2021000100160"]}]},{"name":"NATO Science for Peace and Security Programme","award":["G6133"],"award-info":[{"award-number":["G6133"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2024,9,9]]},"DOI":"10.1145\/3678232.3678240","type":"proceedings-article","created":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T22:35:17Z","timestamp":1725489317000},"page":"1-14","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Model Checking and Synthesis for Strategic Timed CTL using Strategies in Rewriting Logic"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-3019-4902","authenticated-orcid":false,"given":"Jaime","family":"Arias","sequence":"first","affiliation":[{"name":"Universit\u00e9 Sorbonne Paris Nord, LIPN, CNRS UMR 7030, France"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7264-7773","authenticated-orcid":false,"given":"Carlos","family":"Olarte","sequence":"additional","affiliation":[{"name":"Universit\u00e9 Sorbonne Paris Nord, LIPN, CNRS UMR 7030, France"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6477-4863","authenticated-orcid":false,"given":"Wojciech","family":"Penczek","sequence":"additional","affiliation":[{"name":"Warsaw University of Technology, Poland"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3154-5268","authenticated-orcid":false,"given":"Laure","family":"Petrucci","sequence":"additional","affiliation":[{"name":"Universit\u00e9 Sorbonne Paris Nord, LIPN, CNRS UMR 7030, France"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4393-3447","authenticated-orcid":false,"given":"Teofil","family":"Sidoruk","sequence":"additional","affiliation":[{"name":"Warsaw University of Technology, Poland"}]}],"member":"320","published-online":{"date-parts":[[2024,9,9]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1006\/inco.1993.1024"},{"volume-title":"ICALP(LNCS, Vol.\u00a0443)","author":"Alur Rajeev","key":"e_1_3_2_1_2_1","unstructured":"Rajeev Alur and David\u00a0L. Dill. 1990. Automata For Modeling Real-Time Systems. In ICALP(LNCS, Vol.\u00a0443). Springer, 322\u2013335."},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1006\/inco.1993.1025"},{"volume-title":"Alternating-time Temporal Logic","author":"Alur Rajeev","key":"e_1_3_2_1_4_1","unstructured":"Rajeev Alur, Thomas\u00a0A. Henzinger, and Orna Kupferman. 1997. Alternating-time Temporal Logic. In FOCS. IEEE Computer Society, 100\u2013109."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/585265.585270"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1007\/s10009-017-0467-0"},{"volume-title":"CAV (1)(LNCS, Vol.\u00a012759)","author":"Andr\u00e9 \u00c9tienne","key":"e_1_3_2_1_7_1","unstructured":"\u00c9tienne Andr\u00e9. 2021. IMITATOR 3: Synthesis of Timing Parameters Beyond Decidability. In CAV (1)(LNCS, Vol.\u00a012759). Springer, 552\u2013565."},{"key":"e_1_3_2_1_8_1","volume-title":"Controlling Actions and Time in Parametric Timed Automata. In ACSD","author":"Andr\u00e9 \u00c9tienne","year":"2016","unstructured":"\u00c9tienne Andr\u00e9, Michal Knapik, Wojciech Penczek, and Laure Petrucci. 2016. Controlling Actions and Time in Parametric Timed Automata. In ACSD 2016, J\u00f6rg Desel and Alex Yakovlev (Eds.). IEEE Computer Society, 45\u201354."},{"volume-title":"TAP 2021(LNCS, Vol.\u00a012740), Fr\u00e9d\u00e9ric Loulergue and Franz Wotawa (Eds.)","author":"Andr\u00e9 \u00c9tienne","key":"e_1_3_2_1_9_1","unstructured":"\u00c9tienne Andr\u00e9, Dylan Marinho, and Jaco van\u00a0de Pol. 2021. A Benchmarks Library for Extended Parametric Timed Automata. In TAP 2021(LNCS, Vol.\u00a012740), Fr\u00e9d\u00e9ric Loulergue and Franz Wotawa (Eds.). Springer, 39\u201350."},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"crossref","unstructured":"Jaime Arias Kyungmin Bae Carlos Olarte Peter\u00a0Csaba \u00d6lveczky Laure Petrucci and Fredrik R\u00f8mming. 2022. Rewriting Logic Semantics and Symbolic Analysis for Parametric Timed Automata. In FTSCS. ACM 3\u201315.","DOI":"10.1145\/3563822.3569923"},{"key":"e_1_3_2_1_11_1","volume-title":"Symbolic Analysis and Parameter Synthesis for Networks of Parametric Timed Automata with Global Variables using Maude and SMT Solving. Science of Computer Programming","author":"Arias Jaime","year":"2023","unstructured":"Jaime Arias, Kyungmin Bae, Carlos Olarte, Peter\u00a0Csaba \u00d6lveczky, Laure Petrucci, and Fredrik R\u00f8mming. 2023. Symbolic Analysis and Parameter Synthesis for Networks of Parametric Timed Automata with Global Variables using Maude and SMT Solving. Science of Computer Programming (2023). To appear."},{"volume-title":"Petri Nets(LNCS, Vol.\u00a013929)","author":"Arias Jaime","key":"e_1_3_2_1_12_1","unstructured":"Jaime Arias, Kyungmin Bae, Carlos Olarte, Peter\u00a0Csaba \u00d6lveczky, Laure Petrucci, and Fredrik R\u00f8mming. 2023. Symbolic Analysis and Parameter Synthesis for Time Petri Nets Using Maude and SMT Solving. In Petri Nets(LNCS, Vol.\u00a013929). Springer, 369\u2013392."},{"key":"e_1_3_2_1_13_1","unstructured":"Jaime Arias Wojciech Jamroga Wojciech Penczek Laure Petrucci and Teofil Sidoruk. 2023. Strategic (Timed) Computation Tree Logic. In AAMAS. ACM 382\u2013390."},{"key":"e_1_3_2_1_14_1","unstructured":"Jaime Arias Carlos Olarte Wojciech Penczek Laure Petrucci and Teofil Sidoruk. 2024. Model Checking and Synthesis for STCTL using Rewriting Logic. https:\/\/depot.lipn.univ-paris13.fr\/mosart\/tools\/maude-stctl"},{"volume-title":"Principles of model checking","author":"Baier Christel","key":"e_1_3_2_1_15_1","unstructured":"Christel Baier and Joost-Pieter Katoen. 2008. Principles of model checking. MIT Press."},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.24963\/ijcai.2019\/13"},{"volume-title":"M4M(ENTCS, Vol.\u00a0231)","author":"Bouyer Patricia","key":"e_1_3_2_1_17_1","unstructured":"Patricia Bouyer. 2007. Model-checking Timed Temporal Logics. In M4M(ENTCS, Vol.\u00a0231). Elsevier, 323\u2013341."},{"volume-title":"Sequential Circuit Verification Using Symbolic Model Checking","author":"Burch R.","key":"e_1_3_2_1_18_1","unstructured":"Jerry\u00a0R. Burch, Edmund\u00a0M. Clarke, Kenneth\u00a0L. McMillan, and David\u00a0L. Dill. 1990. Sequential Circuit Verification Using Symbolic Model Checking. In DAC. IEEE Computer Society Press, 46\u201351."},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/363516.363528"},{"key":"e_1_3_2_1_20_1","unstructured":"Manuel Clavel Francisco Dur\u00e1n Steven Eker Patrick Lincoln Narciso Mart\u00ed-Oliet Jos\u00e9 Meseguer and Carolyn\u00a0L. Talcott (Eds.). 2007. All About Maude - A High-Performance Logical Framework How to Specify Program and Verify Systems in Rewriting Logic. LNCS Vol.\u00a04350. Springer."},{"volume-title":"CADE(LNCS, Vol.\u00a09195)","author":"David Am\u00e9lie","key":"e_1_3_2_1_21_1","unstructured":"Am\u00e9lie David. 2015. Deciding ATL*\u2009Satisfiability by Tableaux. In CADE(LNCS, Vol.\u00a09195). Springer, 214\u2013228."},{"key":"e_1_3_2_1_22_1","volume-title":"Programming and symbolic computation in Maude. J. Log. Algebraic Methods Program. 110","author":"Dur\u00e1n Francisco","year":"2020","unstructured":"Francisco Dur\u00e1n, Steven Eker, Santiago Escobar, Narciso Mart\u00ed-Oliet, Jos\u00e9 Meseguer, Rub\u00e9n Rubio, and Carolyn\u00a0L. Talcott. 2020. Programming and symbolic computation in Maude. J. Log. Algebraic Methods Program. 110 (2020)."},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.jlamp.2023.100887"},{"volume-title":"Reasoning About Knowledge","author":"Fagin Ronald","key":"e_1_3_2_1_24_1","unstructured":"Ronald Fagin, Joseph\u00a0Y. Halpern, Yoram Moses, and Moshe\u00a0Y. Vardi. 1995. Reasoning About Knowledge. MIT Press."},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/1614431.1614434"},{"key":"e_1_3_2_1_26_1","volume-title":"ChatGPT is not all you need. A State of the Art Review of large Generative AI models. CoRR abs\/2301.04655","author":"Gozalo-Brizuela Roberto","year":"2023","unstructured":"Roberto Gozalo-Brizuela and Eduardo\u00a0C. Garrido-Merch\u00e1n. 2023. ChatGPT is not all you need. A State of the Art Review of large Generative AI models. CoRR abs\/2301.04655 (2023)."},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/32.940728"},{"volume-title":"FME(LNCS, Vol.\u00a01051)","author":"Havelund Klaus","key":"e_1_3_2_1_28_1","unstructured":"Klaus Havelund and Natarajan Shankar. 1996. Experiments in Theorem Proving and Model Checking for Protocol Verification. In FME(LNCS, Vol.\u00a01051). Springer, 662\u2013681."},{"volume-title":"WRS@FLoC 2006(ENTCS, Vol.\u00a0174)","author":"Hidalgo-Herrero Mercedes","key":"e_1_3_2_1_29_1","unstructured":"Mercedes Hidalgo-Herrero, Alberto Verdejo, and Yolanda Ortega-Mall\u00e9n. 2006. Using Maude and Its Strategies for Defining a Framework for Analyzing Eden Semantics. In WRS@FLoC 2006(ENTCS, Vol.\u00a0174), Sergio Antoy (Ed.). Elsevier, 119\u2013137."},{"key":"e_1_3_2_1_30_1","volume-title":"Holzmann and Rajeev Joshi","author":"J.","year":"2004","unstructured":"Gerard\u00a0J. Holzmann and Rajeev Joshi. 2004. Model-Driven Software Verification. In SPIN(LNCS, Vol.\u00a02989). Springer, 76\u201391."},{"volume-title":"Symbolic Model Checking Epistemic Strategy Logic","author":"Huang Xiaowei","key":"e_1_3_2_1_31_1","unstructured":"Xiaowei Huang and Ron van\u00a0der Meyden. 2014. Symbolic Model Checking Epistemic Strategy Logic. In AAAI. AAAI Press, 1426\u20131432."},{"key":"e_1_3_2_1_32_1","unstructured":"Wojciech Jamroga Michal Knapik and Damian Kurpiewski. 2017. Fixpoint Approximation of Strategic Abilities under Imperfect Information. In AAMAS. ACM 1241\u20131249."},{"key":"e_1_3_2_1_33_1","volume-title":"Approximate verification of strategic abilities under imperfect information. Artif. Intell. 277","author":"Jamroga Wojciech","year":"2019","unstructured":"Wojciech Jamroga, Michal Knapik, Damian Kurpiewski, and Lukasz Mikulski. 2019. Approximate verification of strategic abilities under imperfect information. Artif. Intell. 277 (2019)."},{"key":"e_1_3_2_1_34_1","unstructured":"Wojciech Jamroga Beata Konikowska and Wojciech Penczek. 2016. Multi-Valued Verification of Strategic Ability. In AAMAS. ACM 1180\u20131189."},{"key":"e_1_3_2_1_35_1","unstructured":"Wojciech Jamroga Wojciech Penczek Piotr Dembinski and Antoni\u00a0W. Mazurkiewicz. 2018. Towards Partial Order Reductions for Strategic Ability. In AAMAS. IFAAMAS 156\u2013165."},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"crossref","unstructured":"Magdalena Kacprzak Artur Niewiadomski and Wojciech Penczek. 2020. SAT-Based ATL Satisfiability Checking. In KR. 539\u2013549.","DOI":"10.24963\/kr.2020\/54"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"crossref","unstructured":"Magdalena Kacprzak Artur Niewiadomski and Wojciech Penczek. 2021. Satisfiability Checking of Strategy Logic with Simple Goals. In KR. 400\u2013410.","DOI":"10.24963\/kr.2021\/38"},{"volume-title":"SMT-Based Satisfiability Checking of Strategic Metric Temporal Logic","author":"Kacprzak Magdalena","key":"e_1_3_2_1_38_1","unstructured":"Magdalena Kacprzak, Artur Niewiadomski, Wojciech Penczek, and Andrzej Zbrzezny. 2023. SMT-Based Satisfiability Checking of Strategic Metric Temporal Logic. In ECAI. IOS Press, 1180\u20131189."},{"volume-title":"Unbounded Model Checking for Alternating-Time Temporal Logic","author":"Kacprzak Magdalena","key":"e_1_3_2_1_39_1","unstructured":"Magdalena Kacprzak and Wojciech Penczek. 2004. Unbounded Model Checking for Alternating-Time Temporal Logic. In AAMAS. IEEE Computer Society, 646\u2013653."},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1007\/s10458-005-0944-9"},{"volume-title":"VECoS(LNCS, Vol.\u00a013187)","author":"Kanski Michal","key":"e_1_3_2_1_41_1","unstructured":"Michal Kanski, Artur Niewiadomski, Magdalena Kacprzak, Wojciech Penczek, and Wojciech Nabialek. 2021. SMT-Based Unbounded Model Checking for ATL. In VECoS(LNCS, Vol.\u00a013187). Springer, 43\u201358."},{"volume-title":"CAV (1)(LNCS, Vol.\u00a09779)","author":"Klenze Tobias","key":"e_1_3_2_1_42_1","unstructured":"Tobias Klenze, Sam Bayless, and Alan\u00a0J. Hu. 2016. Fast, Flexible, and Minimal CTL Synthesis via SMT. In CAV (1)(LNCS, Vol.\u00a09779). Springer, 136\u2013156."},{"volume-title":"FORMATS(LNCS, Vol.\u00a04202)","author":"Laroussinie Fran\u00e7ois","key":"e_1_3_2_1_43_1","unstructured":"Fran\u00e7ois Laroussinie, Nicolas Markey, and Ghassan Oreiby. 2006. Model-Checking Timed ATL for Durational Concurrent Game Structures. In FORMATS(LNCS, Vol.\u00a04202). Springer, 245\u2013259."},{"key":"e_1_3_2_1_44_1","doi-asserted-by":"crossref","unstructured":"Alessio Lomuscio Wojciech Penczek and Hongyang Qu. 2010. Partial order reductions for model checking temporal epistemic logics over interleaved multi-agent systems. In AAMAS. IFAAMAS 659\u2013666.","DOI":"10.3233\/FI-2010-276"},{"key":"e_1_3_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.3233\/FI-2010-276"},{"key":"e_1_3_2_1_46_1","doi-asserted-by":"publisher","DOI":"10.1007\/s10009-015-0378-x"},{"key":"e_1_3_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.1016\/0304-3975(92)90182-F"},{"key":"e_1_3_2_1_48_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.jlap.2012.06.003"},{"key":"e_1_3_2_1_49_1","unstructured":"Artur Niewiadomski Magdalena Kacprzak Damian Kurpiewski Michal Knapik Wojciech Penczek and Wojciech Jamroga. 2020. MsATL: A Tool for SAT-Based ATL Satisfiability Checking. In AAMAS. IFAAMAS 2111\u20132113."},{"key":"e_1_3_2_1_50_1","volume-title":"AAMAS","author":"Niewiadomski Artur","year":"2024","unstructured":"Artur Niewiadomski, Maciej Nazarczuk, Mateusz Przychodzki, Magdalena Kacprzak, Wojciech Penczek, and Andrzej Zbrzezny. 2024. SMT4SMTL: A Tool for SMT-Based Satisfiability Checking of SMTL. In AAMAS 2024, Mehdi Dastani, Jaime\u00a0Sim\u00e3o Sichman, Natasha Alechina, and Virginia Dignum (Eds.). ACM, 2815\u20132817."},{"key":"e_1_3_2_1_51_1","volume-title":"14th International Conference, TACAS 2008(LNCS, Vol.\u00a04963)","author":"\u00d6lveczky Peter\u00a0Csaba","year":"2008","unstructured":"Peter\u00a0Csaba \u00d6lveczky and Jos\u00e9 Meseguer. 2008. The Real-Time Maude Tool. In Tools and Algorithms for the Construction and Analysis of Systems, 14th International Conference, TACAS 2008(LNCS, Vol.\u00a04963), C.\u00a0R. Ramakrishnan and Jakob Rehof (Eds.). Springer, 332\u2013336."},{"key":"e_1_3_2_1_52_1","unstructured":"Wojciech Penczek. 2018. Improving Efficiency of Model Checking for Variants of Alternating-time Temporal Logic. In CS&P(CEUR Vol.\u00a02240). CEUR-WS.org."},{"volume-title":"Vol.\u00a020","author":"Penczek Wojciech","key":"e_1_3_2_1_53_1","unstructured":"Wojciech Penczek and Agata P\u00f3lrola. 2006. Advances in Verification of Time Petri Nets and Timed Automata: A Temporal Logic Approach. Studies in Computational Intelligence, Vol.\u00a020. Springer."},{"key":"e_1_3_2_1_54_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.jlamp.2016.10.001"},{"volume-title":"RULE@RDP 2005(ENTCS, Vol.\u00a0147), Horatiu Cirstea and Narciso Mart\u00ed-Oliet (Eds.)","author":"Rosa-Velardo Fernando","key":"e_1_3_2_1_55_1","unstructured":"Fernando Rosa-Velardo, Clara Segura, and Alberto Verdejo. 2005. Typed Mobile Ambients in Maude. In RULE@RDP 2005(ENTCS, Vol.\u00a0147), Horatiu Cirstea and Narciso Mart\u00ed-Oliet (Eds.). Elsevier, 135\u2013161."},{"key":"e_1_3_2_1_56_1","doi-asserted-by":"publisher","DOI":"10.1007\/s10515-021-00307-9"},{"key":"e_1_3_2_1_57_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.jlamp.2021.100727"},{"key":"e_1_3_2_1_58_1","volume-title":"Rewriting Logic Using Strategies for Neural Networks: An Implementation in Maude. In DCAI 2008(Advances in Soft Computing, Vol.\u00a050)","author":"Santos-Garc\u00eda Gustavo","year":"2008","unstructured":"Gustavo Santos-Garc\u00eda, Miguel Palomino, and Alberto Verdejo. 2008. Rewriting Logic Using Strategies for Neural Networks: An Implementation in Maude. In DCAI 2008(Advances in Soft Computing, Vol.\u00a050), Juan\u00a0M. Corchado, Sara Rodr\u00edguez, James Llinas, and Jos\u00e9\u00a0M. Molina (Eds.). Springer, 424\u2013433."},{"volume-title":"Validating Requirements for Fault Tolerant Systems using Model Checking","author":"Schneider Francis","key":"e_1_3_2_1_59_1","unstructured":"Francis Schneider, Steve\u00a0M. Easterbrook, John\u00a0R. Callahan, and Gerard\u00a0J. Holzmann. 1998. Validating Requirements for Fault Tolerant Systems using Model Checking. In ICRE. IEEE Computer Society, 4\u201313."},{"volume-title":"LCMAS(ENTCS, Vol.\u00a085)","author":"Schobbens Pierre-Yves","key":"e_1_3_2_1_60_1","unstructured":"Pierre-Yves Schobbens. 2003. Alternating-time logic with imperfect recall. In LCMAS(ENTCS, Vol.\u00a085). Elsevier, 82\u201393."},{"key":"e_1_3_2_1_61_1","doi-asserted-by":"publisher","DOI":"10.1145\/2660267.2660315"},{"volume-title":"CADE 29(LNCS, Vol.\u00a014132)","author":"Whitters Gerald","key":"e_1_3_2_1_62_1","unstructured":"Gerald Whitters, Vivek Nigam, and Carolyn\u00a0L. Talcott. 2023. Incremental Rewriting Modulo SMT. In CADE 29(LNCS, Vol.\u00a014132), Brigitte Pientka and Cesare Tinelli (Eds.). Springer, 560\u2013576."},{"key":"e_1_3_2_1_63_1","doi-asserted-by":"crossref","unstructured":"Thomas Witkowski Nicolas Blanc Daniel Kroening and Georg Weissenbacher. 2007. Model checking concurrent Linux device drivers. In ASE. ACM 501\u2013504.","DOI":"10.1145\/1321631.1321719"}],"event":{"name":"PPDP 2024: 26th International Symposium on Principles and Practice of Declarative Programming","acronym":"PPDP 2024","location":"Milano Italy"},"container-title":["Proceedings of the 26th International Symposium on Principles and Practice of Declarative Programming"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3678232.3678240","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3678232.3678240","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T22:54:09Z","timestamp":1750287249000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3678232.3678240"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,9,9]]},"references-count":63,"alternative-id":["10.1145\/3678232.3678240","10.1145\/3678232"],"URL":"https:\/\/doi.org\/10.1145\/3678232.3678240","relation":{},"subject":[],"published":{"date-parts":[[2024,9,9]]},"assertion":[{"value":"2024-09-09","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}