{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,10,2]],"date-time":"2026-10-02T08:03:49Z","timestamp":1790928229671,"version":"4.1.0"},"reference-count":36,"publisher":"Association for Computing Machinery (ACM)","issue":"OOPSLA2","license":[{"start":{"date-parts":[[2024,10,8]],"date-time":"2024-10-08T00:00:00Z","timestamp":1728345600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"NSF","award":["1955688"],"award-info":[{"award-number":["1955688"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["Proc. ACM Program. Lang."],"published-print":{"date-parts":[[2024,10,8]]},"abstract":"<jats:p>A superoptimizing compiler\u2014one that performs a meaningful search of the program space as part of the optimization process\u2014can find optimization opportunities that are missed by even the best existing optimizing compilers. We created Minotaur: a superoptimizer for LLVM that uses program synthesis to improve its code generation, focusing on integer and floating-point SIMD code. On an Intel Cascade Lake processor, Minotaur achieves an average speedup of 7.3% on the GNU Multiple Precision library (GMP)\u2019s benchmark suite, with a maximum speedup of 13%. On SPEC CPU 2017, our superoptimizer produces an average speedup of 1.5%, with a maximum speedup of 4.5% for 638.imagick. Every optimization produced by Minotaur has been formally verified, and several optimizations that it has discovered have been implemented in LLVM as a result of our work.<\/jats:p>","DOI":"10.1145\/3689766","type":"journal-article","created":{"date-parts":[[2024,10,8]],"date-time":"2024-10-08T03:23:04Z","timestamp":1728357784000},"page":"1561-1585","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":10,"title":["Minotaur: A SIMD-Oriented Synthesizing Superoptimizer"],"prefix":"10.1145","volume":"8","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-4938-1935","authenticated-orcid":false,"given":"Zhengyang","family":"Liu","sequence":"first","affiliation":[{"name":"University of Utah, Salt Lake City, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0006-8473-3667","authenticated-orcid":false,"given":"Stefan","family":"Mada","sequence":"additional","affiliation":[{"name":"University of Utah, Salt Lake City, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7025-4610","authenticated-orcid":false,"given":"John","family":"Regehr","sequence":"additional","affiliation":[{"name":"University of Utah, Salt Lake City, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2024,10,8]]},"reference":[{"key":"e_1_3_1_2_2","doi-asserted-by":"crossref","unstructured":"Maaz Bin Safeer Ahmad Alexander J. Root Andrew Adams Shoaib Kamil and Alvin Cheung. 2022. Vector Instruction Selection for Digital Signal Processors Using Program Synthesis. In Proceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (Lausanne Switzerland) (ASPLOS 2022). 1004-1016. https:\/\/doi.org\/10.1145\/3503222.3507714 10.1145\/3503222.3507714","DOI":"10.1145\/3503222.3507714"},{"key":"e_1_3_1_3_2","unstructured":"AMD. 2023. AMD Zen 3. https:\/\/www.amd.com\/en\/technologies\/zen-core."},{"key":"e_1_3_1_4_2","unstructured":"ARM. 2023. ARM NEON Architecture. https:\/\/developer.arm.com\/Architectures\/Neon."},{"key":"e_1_3_1_5_2","doi-asserted-by":"publisher","DOI":"10.1145\/1168857.1168906"},{"key":"e_1_3_1_6_2","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-662-46663-6_9"},{"key":"e_1_3_1_7_2","doi-asserted-by":"crossref","unstructured":"Yishen Chen Charith Mendis Michael Carbin and Saman Amarasinghe. 2021. VeGen: A Vectorizer Generator for SIMD and Beyond. 902-914. https:\/\/doi.org\/10.1145\/3445814.3446692 10.1145\/3445814.3446692","DOI":"10.1145\/3445814.3446692"},{"key":"e_1_3_1_8_2","doi-asserted-by":"publisher","DOI":"10.1145\/3368826.3377912"},{"key":"e_1_3_1_9_2","doi-asserted-by":"publisher","DOI":"10.1145\/502874.502885"},{"key":"e_1_3_1_10_2","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-78800-3_24"},{"key":"e_1_3_1_11_2","unstructured":"LLVM Developers. 2023. LLVM Machine Code Analyzer. https:\/\/llvm.org\/docs\/CommandGuide\/llvm-mca.html."},{"key":"e_1_3_1_12_2","unstructured":"Bruno Dutertre . 2015. Solving Exists\/Forall Problems With Yices. In The 13th International Workshop on Satisfiability Modulo Theories."},{"key":"e_1_3_1_13_2","doi-asserted-by":"crossref","unstructured":"Marcos Horro Louis-No\u00ebl Pouchet Gabriel Rodr\u00edguez and Juan Tourino. 2022. Custom High-Performance Vector Code Generation for Data-Specific Sparse Computations. In Proceedings of the 31st International Conference on Parallel Architectures and Compilation Techniques.","DOI":"10.1145\/3559009.3569668"},{"key":"e_1_3_1_14_2","unstructured":"Intel. 2023. Cascade Lake: Overview. https:\/\/www.intel.com\/content\/www\/us\/en\/products\/platforms\/details\/cascade-lake.html."},{"key":"e_1_3_1_15_2","unstructured":"Intel. 2023. Intel Intrinsics Guide. https:\/\/www.intel.com\/content\/www\/us\/en\/docs\/intrinsics-guide\/index.html."},{"key":"e_1_3_1_16_2","doi-asserted-by":"publisher","DOI":"10.1145\/543552.512566"},{"key":"e_1_3_1_17_2","doi-asserted-by":"publisher","DOI":"10.1145\/349299.349320"},{"key":"e_1_3_1_18_2","doi-asserted-by":"publisher","DOI":"10.5555\/977395.977673"},{"key":"e_1_3_1_19_2","unstructured":"LLVM Developers. 2023. LoopInfo. https:\/\/llvm.org\/doxygen\/classllvm_1_1LoopInfo.html."},{"key":"e_1_3_1_20_2","unstructured":"LLVM Developers. 2023. MemorySSA. https:\/\/llvm.org\/docs\/MemorySSA.html."},{"key":"e_1_3_1_21_2","unstructured":"LLVM Developers. 2023. ORC Design and Implementation. https:\/\/llvm.org\/docs\/ORCv2.html."},{"key":"e_1_3_1_22_2","unstructured":"LLVM Developers. 2023. Target Transform Info Class Reference. https:\/\/llvm.org\/doxygen\/classllvm_1_1TargetTransformInfo.html."},{"key":"e_1_3_1_23_2","doi-asserted-by":"crossref","unstructured":"Nuno P. Lopes Juneyoung Lee Chung-Kil Hur Zhengyang Liu and John Regehr. 2021. Alive2: Bounded Translation Validation for LLVM. 65-79. https:\/\/doi.org\/10.1145\/3453483.3454030 10.1145\/3453483.3454030","DOI":"10.1145\/3453483.3454030"},{"key":"e_1_3_1_24_2","doi-asserted-by":"publisher","DOI":"10.1145\/36206.36194"},{"key":"e_1_3_1_25_2","doi-asserted-by":"publisher","DOI":"10.1145\/3297858.3304059"},{"key":"e_1_3_1_26_2","doi-asserted-by":"publisher","DOI":"10.1145\/3150211"},{"key":"e_1_3_1_27_2","unstructured":"Duncan Sands . 2011. Super-optimizing LLVM IR. http:\/\/llvm.org\/devmtg\/2011-11\/Sands_Super-optimizingLLVMIR.pdf Presentation at the 2011 LLVM Developers Meeting."},{"key":"e_1_3_1_28_2","unstructured":"Raimondas Sasnauskas Yang Chen Peter Collingbourne Jeroen Ketema Gratian Lup Jubi Taneja and John Regehr. 2017. Souper: A synthesizing superoptimizer. arXiv preprint arXiv:1711.04422 (2017)."},{"key":"e_1_3_1_29_2","doi-asserted-by":"publisher","DOI":"10.1145\/2451116.2451150"},{"key":"e_1_3_1_30_2","doi-asserted-by":"publisher","DOI":"10.1145\/2666356.2594302"},{"key":"e_1_3_1_31_2","doi-asserted-by":"publisher","DOI":"10.1145\/2858965.2814278"},{"key":"e_1_3_1_32_2","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-10672-9_3"},{"key":"e_1_3_1_33_2","doi-asserted-by":"publisher","DOI":"10.1145\/1480881.1480915"},{"key":"e_1_3_1_34_2","unstructured":"Qualcomm Technologies. [n. d.]. Hexagon DSP SDK. https:\/\/developer.qualcomm.com\/software\/hexagon-dsp-sdk."},{"key":"e_1_3_1_35_2","doi-asserted-by":"publisher","DOI":"10.1145\/2509578.2509586"},{"key":"e_1_3_1_36_2","doi-asserted-by":"publisher","DOI":"10.1145\/3445814.3446707"},{"key":"e_1_3_1_37_2","unstructured":"Jackson Woodruff Thomas Koehler Alexander Brauckmann Chris Cummins Sam Ainsworth and Michael FP O\u2019Boyle. 2023. Rewriting History: Repurposing Domain-Specific CGRAs. arXiv preprint arXiv:2309.09112 (2023)."}],"container-title":["Proceedings of the ACM on Programming Languages"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3689766","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3689766","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,2,4]],"date-time":"2026-02-04T09:03:40Z","timestamp":1770195820000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3689766"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,10,8]]},"references-count":36,"journal-issue":{"issue":"OOPSLA2","published-print":{"date-parts":[[2024,10,8]]}},"alternative-id":["10.1145\/3689766"],"URL":"https:\/\/doi.org\/10.1145\/3689766","relation":{},"ISSN":["2475-1421"],"issn-type":[{"value":"2475-1421","type":"electronic"}],"subject":[],"published":{"date-parts":[[2024,10,8]]},"assertion":[{"value":"2024-04-03","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2024-08-18","order":2,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2024-10-08","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}