{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,11]],"date-time":"2026-03-11T01:44:21Z","timestamp":1773193461941,"version":"3.50.1"},"reference-count":59,"publisher":"Association for Computing Machinery (ACM)","issue":"OOPSLA2","license":[{"start":{"date-parts":[[2024,10,8]],"date-time":"2024-10-08T00:00:00Z","timestamp":1728345600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"DOI":"10.13039\/100000001","name":"NSF","doi-asserted-by":"publisher","award":["1845952, 2124045, 2118709"],"award-info":[{"award-number":["1845952, 2124045, 2118709"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["Proc. ACM Program. Lang."],"published-print":{"date-parts":[[2024,10,8]]},"abstract":"<jats:p>\n                    Compilers for accelerator design languages (ADLs) translate high-level languages into application-specific hardware. ADL compilers rely on a hardware\n                    <jats:italic toggle=\"yes\">control interface<\/jats:italic>\n                    to compose hardware units. There are two choices:\n                    <jats:italic toggle=\"yes\">static<\/jats:italic>\n                    control, which relies on cycle-level timing; or\n                    <jats:italic toggle=\"yes\">dynamic<\/jats:italic>\n                    control, which uses explicit signalling to avoid depending on timing details. Static control is efficient but brittle; dynamic control incurs hardware costs to support compositional reasoning.\n                  <\/jats:p>\n                  <jats:p>\n                    Piezo is an ADL compiler that unifies static and dynamic control in a single intermediate language (IL). Its key insight is that the IL\u2019s static fragment is a\n                    <jats:italic toggle=\"yes\">refinement<\/jats:italic>\n                    of its dynamic fragment: static code admits a subset of the run-time behaviors of the dynamic equivalent. Piezo can optimize code by combining facts from static and dynamic submodules, and it opportunistically converts code from dynamic to static control styles. We implement Piezo as an extension to an existing dynamic ADL compiler, Calyx. We use Piezo to implement a frontend for an existing ADL, a systolic array generator, and a packet-scheduling hardware generator to demonstrate its optimizations and the static\u2013dynamic interactions it enables.\n                  <\/jats:p>","DOI":"10.1145\/3689790","type":"journal-article","created":{"date-parts":[[2024,10,8]],"date-time":"2024-10-08T03:23:04Z","timestamp":1728357784000},"page":"2242-2267","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["Unifying Static and Dynamic Intermediate Languages for Accelerator Generators"],"prefix":"10.1145","volume":"8","author":[{"ORCID":"https:\/\/orcid.org\/0009-0005-1832-6943","authenticated-orcid":false,"given":"Caleb","family":"Kim","sequence":"first","affiliation":[{"name":"Cornell University, Ithaca, USA"}]},{"ORCID":"https:\/\/orcid.org\/0009-0001-7583-5024","authenticated-orcid":false,"given":"Pai","family":"Li","sequence":"additional","affiliation":[{"name":"Cornell University, Ithaca, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6803-9767","authenticated-orcid":false,"given":"Anshuman","family":"Mohan","sequence":"additional","affiliation":[{"name":"Cornell University, Ithaca, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6528-4281","authenticated-orcid":false,"given":"Andrew","family":"Butt","sequence":"additional","affiliation":[{"name":"Cornell University, Ithaca, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0837-8924","authenticated-orcid":false,"given":"Adrian","family":"Sampson","sequence":"additional","affiliation":[{"name":"Cornell University, Ithaca, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0983-5867","authenticated-orcid":false,"given":"Rachit","family":"Nigam","sequence":"additional","affiliation":[{"name":"Cornell University, Ithaca, USA"}]}],"member":"320","published-online":{"date-parts":[[2024,10,8]]},"reference":[{"key":"e_1_3_1_2_1","unstructured":"AMD Inc. 2021. Vivado Design Suite User Guide: Synthesis. UG901 (v2017.2) June 7 2017. Retrieved November 19 2021 from https:\/\/www.xilinx.com\/support\/documentation\/sw_manuals\/xilinx2017_2\/ug901-vivado-synthesis.pdf"},{"key":"e_1_3_1_3_1","unstructured":"C Scott Ananian. 1998. Silicon C: A Hardware Backend for SUIF. https:\/\/flex.cscott.net\/SiliconC\/."},{"key":"e_1_3_1_4_1","doi-asserted-by":"crossref","unstructured":"Griffin Berlstein Rachit Nigam Christophe Gyurgyik and Adrian Sampson. 2023. Stepwise Debugging for Hardware Accelerators. In Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS). https:\/\/doi.org\/10.1145\/3575693.3575717 10.1145\/3575693.3575717","DOI":"10.1145\/3575693.3575717"},{"key":"e_1_3_1_5_1","unstructured":"Cadence. 2024. Stratus High-Level Synthesis. https:\/\/www.cadence.com\/content\/cadence-www\/global\/en_US\/home\/tools\/digital-design-and-signoff\/synthesis\/stratus-high-level-synthesis.html"},{"key":"e_1_3_1_6_1","doi-asserted-by":"crossref","unstructured":"Andrew Canis Jongsok Choi Mark Aldham Victor Zhang Ahmed Kammoona Jason H Anderson Stephen Brown and Tomasz Czajkowski. 2011. LegUp: High-level synthesis for FPGA-based processor\/accelerator systems. https:\/\/doi.org\/10.1145\/1950413.1950423 10.1145\/1950413.1950423","DOI":"10.1145\/1950413.1950423"},{"key":"e_1_3_1_7_1","article-title":"Allo: A Programming Model for Composable Accelerator Design","volume":"8","author":"Chen Hongzheng","year":"2024","unstructured":"Hongzheng Chen, Niansong Zhang, Shaojie Xiang, Zhichen Zeng, Mengjia Dai, and Zhiru Zhang. 2024. Allo: A Programming Model for Composable Accelerator Design. Proc. ACM Program. Lang. 8, PLDI, Article 171 (jun 2024). https:\/\/doi.org\/10.1145\/3656401 10.1145\/3656401","journal-title":"Proc. ACM Program. Lang."},{"key":"e_1_3_1_8_1","doi-asserted-by":"crossref","unstructured":"Jianyi Cheng Estibaliz Fraca John Wickerson and George A. Constantinides. 2023. Balancing Static Islands in Dynamically Scheduled Circuits Using Continuous Petri Nets. IEEE Trans. Comput. (2023). https:\/\/doi.org\/10.1109\/TC.2023.3292590 10.1109\/TC.2023.3292590","DOI":"10.1109\/TC.2023.3292590"},{"key":"e_1_3_1_9_1","doi-asserted-by":"crossref","unstructured":"Jianyi Cheng Lana Josipovi\u0107 George A. Constantinides Paolo Ienne and John Wickerson. 2020. Combining Dynamic & Static Scheduling in High-Level Synthesis. https:\/\/doi.org\/10.1145\/3373087.3375297 10.1145\/3373087.3375297","DOI":"10.1145\/3373087.3375297"},{"key":"e_1_3_1_10_1","doi-asserted-by":"crossref","unstructured":"Jianyi Cheng John Wickerson and George A. Constantinides. 2022. Finding and Finessing Static Islands in Dynamically Scheduled Circuits. https:\/\/doi.org\/10.1145\/3490422.3502362 10.1145\/3490422.3502362","DOI":"10.1145\/3490422.3502362"},{"key":"e_1_3_1_11_1","doi-asserted-by":"crossref","unstructured":"Jason Cong and Jie Wang. 2018. PolySA:Polyhedral-based systolic arrayauto-compilation. https:\/\/doi.org\/10.1145\/3240765.3240838 10.1145\/3240765.3240838","DOI":"10.1145\/3240765.3240838"},{"key":"e_1_3_1_12_1","doi-asserted-by":"crossref","unstructured":"Tiziano De Matteis Johannes de Fine Licht and Torsten Hoefler. 2020. FBLAS: Streaming Linear Algebra on FPGA. In International Conference for High Performance Computing Networking Storage and Analysis. https:\/\/doi.org\/10.1109\/SC41405.2020.00063 10.1109\/SC41405.2020.00063","DOI":"10.1109\/SC41405.2020.00063"},{"key":"e_1_3_1_13_1","volume-title":"Operational refinement for compiler correctness","author":"Dockins Robert","year":"2012","unstructured":"Robert Dockins. 2012. Operational refinement for compiler correctness. Ph. D. Dissertation. Princeton University."},{"key":"e_1_3_1_14_1","doi-asserted-by":"crossref","unstructured":"Zhen Dong Yizhao Gao Qijing Huang John Wawrzynek Hayden K.H. So and Kurt Keutzer. 2021. HAO: Hardware-aware Neural Architecture Optimization for Efficient Inference. In International Symposium on Field-Programmable Custom Computing Machines (FCCM). https:\/\/doi.org\/10.1109\/FCCM51124.2021.00014 10.1109\/FCCM51124.2021.00014","DOI":"10.1109\/FCCM51124.2021.00014"},{"key":"e_1_3_1_15_1","doi-asserted-by":"crossref","unstructured":"David Durst Matthew Feldman Dillon Huff David Akeley Ross Daly Gilbert Louis Bernstein Marco Patrignani Kayvon Fatahalian and Pat Hanrahan. 2020. Type-Directed Scheduling of Streaming Accelerators. https:\/\/doi.org\/10.1145\/3385412.3385983 10.1145\/3385412.3385983","DOI":"10.1145\/3395633"},{"key":"e_1_3_1_16_1","doi-asserted-by":"crossref","unstructured":"Nate Foster Nick McKeown Jennifer Rexford Guru Parulkar Larry Peterson and Oguz Sunay. 2020. Using Deep Programmability to Put Network Owners in Control. SIGCOMM Comput. Commun. Rev. (2020). https:\/\/doi.org\/10.1145\/3431832.3431842 10.1145\/3431832.3431842","DOI":"10.1145\/3431832.3431842"},{"key":"e_1_3_1_17_1","doi-asserted-by":"crossref","unstructured":"Jeremy Fowers Kalin Ovtcharov Michael Papamichael Todd Massengill Ming Liu Daniel Lo Shlomi Alkalay Michael Haselman Logan Adams Mahdi Ghandi Stephen Heil Prerak Patel Adam Sapek Gabriel Weisz Lisa Woods Sitaram Lanka Steven K. Reinhardt Adrian M. Caulfield Eric S. Chung and Doug Burger. 2018. A Configurable Cloud-scale DNN Processor for Real-time AI. https:\/\/doi.org\/10.1109\/ISCA.2018.00012 10.1109\/ISCA.2018.00012","DOI":"10.1109\/ISCA.2018.00012"},{"key":"e_1_3_1_18_1","volume-title":"Accelerating Halide on an FPGA","author":"Escalfet Sergi Granell","year":"2023","unstructured":"Sergi Granell Escalfet. 2023. Accelerating Halide on an FPGA. Master\u2019s thesis. Universitat Polit\u00e8cnica de Catalunya."},{"key":"e_1_3_1_19_1","doi-asserted-by":"crossref","unstructured":"James Hegarty John Brunhaver Zachary DeVito Jonathan Ragan-Kelley Noy Cohen Steven Bell Artem Vasilyev Mark Horowitz and Pat Hanrahan. 2014. Darkroom: Compiling High-Level Image Processing Code into Hardware Pipelines. ACM Trans. Graph. (2014). https:\/\/doi.org\/10.1145\/2601097.2601174 10.1145\/2601097.2601174","DOI":"10.1145\/2601097.2601174"},{"key":"e_1_3_1_20_1","unstructured":"Intel. 2021. Intel High Level Synthesis Compiler. Retrieved January 16 2021 from https:\/\/www.altera.com\/products\/design-software\/high-level-design\/intel-hls-compiler\/overview.html"},{"key":"e_1_3_1_21_1","unstructured":"Intel. 2024a. Intel Xeon Gold 6230 Processor. Retrieved August 31 2024 from https:\/\/ark.intel.com\/content\/www\/us\/en\/ark\/products\/192437\/intel-xeon-gold-6230-processor-27-5m-cache-2-10-ghz.html"},{"key":"e_1_3_1_22_1","unstructured":"Intel. 2024b. oneAPI Deep Neural Network Library Developer Guide and Reference. https:\/\/oneapi-src.github.io\/oneDNN\/"},{"key":"e_1_3_1_23_1","doi-asserted-by":"crossref","unstructured":"Aihui Jiang Yufeng Li Jiangtao Li and Chenhong Cao. 2022. A Reusable Convolutional Accelerator for CNN on Resourcelimited FPGA. In 2022 IEEE Smartworld Ubiquitous Intelligence & Computing Scalable Computing & Communications Digital Twin Privacy Computing Metaverse Autonomous & Trusted Vehicles (SmartWorld\/UIC\/ScalCom\/DigitalTwin\/PriComp\/Meta). https:\/\/doi.org\/10.1109\/SmartWorld-UIC-ATC-ScalCom-DigitalTwin-PriComp-Metaverse56740.2022.00104 10.1109\/SmartWorld-UIC-ATC-ScalCom-DigitalTwin-PriComp-Metaverse56740.2022.00104","DOI":"10.1109\/SmartWorld-UIC-ATC-ScalCom-DigitalTwin-PriComp-Metaverse56740.2022.00104"},{"key":"e_1_3_1_24_1","doi-asserted-by":"crossref","unstructured":"Lana Josipovi\u0107 Radhika Ghosal and Paolo Ienne. 2018. Dynamically Scheduled High-Level Synthesis. https:\/\/doi.org\/10.1145\/3174243.3174264 10.1145\/3174243.3174264","DOI":"10.1145\/3174243.3174264"},{"key":"e_1_3_1_25_1","doi-asserted-by":"crossref","unstructured":"Norman P. Jouppi Cliff Young Nishant Patil David Patterson Gaurav Agrawal Raminder Bajwa Sarah Bates Suresh Bhatia Nan Boden Al Borchers Rick Boyle Pierre luc Cantin Clifford Chao Chris Clark Jeremy Coriell Mike Daley Matt Dau Jeffrey Dean Ben Gelb Tara Vazir Ghaemmaghami Rajendra Gottipati William Gulland Robert Hagmann C. Richard Ho Doug Hogberg John Hu Robert Hundt Dan Hurt Julian Ibarz Aaron Jaffey Alek Jaworski Alexander Kaplan Harshit Khaitan Andy Koch Naveen Kumar Steve Lacy James Laudon James Law Diemthu Le Chris Leary Zhuyuan Liu Kyle Lucke Alan Lundin Gordon MacKean Adriana Maggiore Maire Mahony Kieran Miller Rahul Nagarajan Ravi Narayanaswami Ray Ni Kathy Nix Thomas Norrie Mark Omernick Narayana Penukonda Andy Phelps Jonathan Ross Matt Ross Amir Salek Emad Samadiani Chris Severn Gregory Sizikov Matthew Snelham Jed Souter Dan Steinberg Andy Swing Mercedes Tan Gregory Thorson Bo Tian Horia Toma Erick Tuttle Vijay Vasudevan Richard Walter Walter Wang Eric Wilcox and Doe Hyun Yoon. 2017. In-Datacenter Performance Analysis of a Tensor Processing Unit. https:\/\/doi.org\/10.1145\/3079856.3080246 10.1145\/3079856.3080246","DOI":"10.1145\/3140659.3080246"},{"key":"e_1_3_1_26_1","unstructured":"Caleb Kim Pai Li Anshuman Mohan Andrew Butt Adrian Sampson and Rachit Nigam. 2024. Reproduction Package for \u201dUnifying Static and Dynamic Intermediate Languages for Accelerator Generators\u201d. https:\/\/doi.org\/10.5281\/zenodo.13388203 10.5281\/zenodo.13388203"},{"key":"e_1_3_1_27_1","doi-asserted-by":"crossref","unstructured":"David Koeplinger Matthew Feldman Raghu Prabhakar Yaqi Zhang Stefan Hadjis Ruben Fiszel Tian Zhao Luigi Nardi Ardavan Pedram Christos Kozyrakis and Kunle Olukotun. 2018. Spatial: A language and compiler for application accelerators. https:\/\/doi.org\/10.1145\/3192366.3192379 10.1145\/3192366.3192379","DOI":"10.1145\/3192366.3192379"},{"key":"e_1_3_1_28_1","doi-asserted-by":"crossref","unstructured":"Hsiang-Tsung Kung. 1982. Why systolic architectures? IEEE Computer (1982). https:\/\/doi.org\/10.1109\/MC.1982.1653825 10.1109\/MC.1982.1653825","DOI":"10.1016\/S0040-4039(00)87034-3"},{"key":"e_1_3_1_29_1","doi-asserted-by":"crossref","unstructured":"Yi-Hsiang Lai Yuze Chi Yuwei Hu Jie Wang Cody Hao Yu Yuan Zhou Jason Cong and Zhiru Zhang. 2019. HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Reconfigurable Computing. https:\/\/doi.org\/10.1145\/3289602.3293910 10.1145\/3289602.3293910","DOI":"10.1145\/3289602.3293910"},{"key":"e_1_3_1_30_1","doi-asserted-by":"crossref","unstructured":"Chris Lattner and Vikram Adve. 2004. LLVM: A Compilation Framework for Lifelong Program Analysis & Transformation. https:\/\/doi.org\/10.1109\/CGO.2004.1281665 10.1109\/CGO.2004.1281665","DOI":"10.1109\/CGO.2004.1281665"},{"key":"e_1_3_1_31_1","doi-asserted-by":"crossref","unstructured":"Chris Lattner Mehdi Amini Uday Bondhugula Albert Cohen Andy Davis Jacques Pienaar River Riddle Tatiana Shpeisman Nicolas Vasilache and Oleksandr Zinenko. 2021. MLIR: Scaling Compiler Infrastructure for Domain Specific Computation. In International Symposium on Code Generation and Optimization (CGO). https:\/\/doi.org\/10.1109\/CGO51591.2021.9370308 10.1109\/CGO51591.2021.9370308","DOI":"10.1109\/CGO51591.2021.9370308"},{"key":"e_1_3_1_32_1","unstructured":"Louis-Noel Pouchet. 2021. PolyBench\/C: The Polyhedral Benchmark Suite. Retrieved January 16 2021 from http:\/\/web.cse.ohio-state.edu\/~pouchet.2\/software\/polybench\/"},{"key":"e_1_3_1_33_1","unstructured":"Andrew L. Maas Awni Y. Hannun and Andrew Y. Ng. 2013. Rectifier Nonlinearities Improve Neural Network Acoustic Models."},{"key":"e_1_3_1_34_1","doi-asserted-by":"crossref","unstructured":"Kingshuk Majumder and Uday Bondhugula. 2024. HIR: An MLIR-based Intermediate Representation for Hardware Accelerator Description. https:\/\/doi.org\/10.1145\/3623278.3624767 10.1145\/3623278.3624767","DOI":"10.1145\/3623278.3624767"},{"key":"e_1_3_1_35_1","unstructured":"Mentor Graphics. 2021. Catapult High-Level Synthesis. Retrieved January 16 2021 from https:\/\/www.mentor.com\/hls-lp\/catapult-high-level-synthesis\/"},{"issue":"2","key":"e_1_3_1_36_1","first-page":"25","article-title":"Formal Abstractions for Packet Scheduling","volume":"7","author":"Mohan Anshuman","year":"2023","unstructured":"Anshuman Mohan, Yunhe Liu, Nate Foster, Tobias Kapp\u00e9, and Dexter Kozen. 2023. Formal Abstractions for Packet Scheduling. Proc. ACM Program. Lang. 7, OOPSLA2, Article 269 (2023), 25 pages. https:\/\/doi.org\/10.1145\/3622845 10.1145\/3622845","journal-title":"Proc. ACM Program. Lang"},{"key":"e_1_3_1_37_1","doi-asserted-by":"crossref","unstructured":"Kevin E. Murray and Vaughn Betz. 2014. Quantifying the Cost and Benefit of Latency Insensitive Communication on FPGAs. https:\/\/doi.org\/10.1145\/2554688.2554786 10.1145\/2554688.2554786","DOI":"10.1145\/2554688.2554786"},{"key":"e_1_3_1_38_1","doi-asserted-by":"crossref","unstructured":"Rachit Nigam Sachille Atapattu Samuel Thomas Zhijing Li Theodore Bauer Yuwei Ye Apurva Koti Adrian Sampson and Zhiru Zhang. 2020. Predictable Accelerator Design with Time-Sensitive Affine Types. https:\/\/doi.org\/10.1145\/3385412.3385974 10.1145\/3385412.3385974","DOI":"10.1145\/3395657"},{"key":"e_1_3_1_39_1","doi-asserted-by":"crossref","unstructured":"Rachit Nigam Pedro Henrique Azevedo de Amorim and Adrian Sampson. 2023. Modular Hardware Design with Timeline Types. https:\/\/doi.org\/10.1145\/3591234 10.1145\/3591234","DOI":"10.1145\/3591234"},{"key":"e_1_3_1_40_1","doi-asserted-by":"crossref","unstructured":"Rachit Nigam Samuel Thomas Zhijing Li and Adrian Sampson. 2021. A compiler infrastructure for accelerator generators. https:\/\/doi.org\/10.1145\/3445814.3446712 10.1145\/3445814.3446712","DOI":"10.1145\/3445814.3446712"},{"key":"e_1_3_1_41_1","doi-asserted-by":"crossref","unstructured":"Christian Pilato and Fabrizio Ferrandi. 2013. Bambu: A modular framework for the high level synthesis of memory-intensive applications. https:\/\/doi.org\/10.1109\/FPL.2013.6645550 10.1109\/FPL.2013.6645550","DOI":"10.1109\/FPL.2013.6645550"},{"key":"e_1_3_1_42_1","doi-asserted-by":"crossref","unstructured":"Jing Pu Steven Bell Xuan Yang Jeff Setter Stephen Richardson Jonathan Ragan-Kelley and Mark Horowitz. 2017. Programming Heterogeneous Systems from an Image Processing DSL. ACM Trans. Archit. Code Optim. (2017). https:\/\/doi.org\/10.1145\/3107953 10.1145\/3107953","DOI":"10.1145\/3107953"},{"key":"e_1_3_1_43_1","doi-asserted-by":"crossref","unstructured":"Jonathan Ragan-Kelley Connelly Barnes Andrew Adams Sylvain Paris Fr\u00e9do Durand and Saman P. Amarasinghe. 2013. Halide: A language and compiler for optimizing parallelism locality and recomputation in image processing pipelines. https:\/\/doi.org\/10.1145\/2491956.2462176 10.1145\/2491956.2462176","DOI":"10.1145\/2491956.2462176"},{"key":"e_1_3_1_44_1","doi-asserted-by":"crossref","unstructured":"Sameer D Sahasrabuddhe Hakim Raja Kavi Arya and Madhav P Desai. 2007. AHIR: A hardware intermediate representation for hardware generation from high-level programs. https:\/\/doi.org\/10.1109\/VLSID.2007.28 10.1109\/VLSID.2007.28","DOI":"10.1109\/VLSID.2007.28"},{"key":"e_1_3_1_45_1","doi-asserted-by":"crossref","unstructured":"Amirali Sharifian Reza Hojabr Navid Rahimi Sihao Liu Apala Guha Tony Nowatzki and Arrvindh Shriraman. 2019. \u03bcIR: An Intermediate Representation for Transforming and Optimizing the Microarchitecture of Application Accelerators. https:\/\/doi.org\/10.1145\/3352460.3358292 10.1145\/3352460.3358292","DOI":"10.1145\/3352460.3358292"},{"key":"e_1_3_1_46_1","doi-asserted-by":"crossref","unstructured":"Rohit Sinha and Hiren Patel. 2012. synASM: A High-Level Synthesis Framework With Support for Parallel and Timed Constructs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2012). https:\/\/doi.org\/10.1109\/TCAD.2012.2198474 10.1109\/TCAD.2012.2198474","DOI":"10.1109\/TCAD.2012.2198474"},{"key":"e_1_3_1_47_1","doi-asserted-by":"publisher","DOI":"10.1145\/2934872.2934899"},{"key":"e_1_3_1_48_1","doi-asserted-by":"crossref","unstructured":"Sam Skalicky Sonia L\u00f3pez Marcin Lukowiak James Letendre and David Gasser. 2013. Linear algebra Computations in Heterogeneous Systems. In Conference on Application-Specific Systems Architectures and Processors. https:\/\/doi.org\/10.1109\/ASAP.2013.6567589 10.1109\/ASAP.2013.6567589","DOI":"10.1109\/ASAP.2013.6567589"},{"key":"e_1_3_1_49_1","doi-asserted-by":"crossref","unstructured":"Robert Szafarczyk Syed Waqar Nabi and Wim Vanderbauwhede. 2023. Compiler Discovered Dynamic Scheduling of Irregular Code in High-Level Synthesis. https:\/\/doi.org\/10.1109\/FPL60245.2023.00009 10.1109\/FPL60245.2023.00009","DOI":"10.1109\/FPL60245.2023.00009"},{"key":"e_1_3_1_50_1","unstructured":"The Calyx Authors. 2022. Disable top-down-st from default compilation pipeline. Retrieved March 8 2022 from https:\/\/github.com\/calyxir\/calyx\/pull\/941"},{"key":"e_1_3_1_51_1","unstructured":"The Calyx Authors. 2023a. Compress static FSMs. Retrieved November 22 2023 from https:\/\/github.com\/cucapra\/calyx\/issues\/936"},{"key":"e_1_3_1_52_1","unstructured":"The Calyx Authors. 2023b. Fix top-down static timing. Retrieved November 22 2023 from https:\/\/github.com\/cucapra\/calyx\/pull\/1338"},{"key":"e_1_3_1_53_1","unstructured":"The Calyx Authors. 2023c. Problems with static FSMs. Retrieved November 22 2023 from https:\/\/github.com\/cucapra\/calyx\/issues\/940"},{"key":"e_1_3_1_54_1","unstructured":"The Piezo Authors. 2024. Piezo Source Code. https:\/\/github.com\/calyxir\/calyx"},{"key":"e_1_3_1_55_1","unstructured":"Mike Urbach and Morten B. Petersen. 2022. HLS from PyTorch to System Verilog with MLIR and CIRCT. In Workshop on Languages Tools and Techniques for Accelerator Design (LATTE)."},{"key":"e_1_3_1_56_1","unstructured":"Veripool. 2021. Verilator. https:\/\/www.veripool.org\/wiki\/verilator."},{"key":"e_1_3_1_57_1","doi-asserted-by":"crossref","unstructured":"Jiahui Xu Emmet Murphy Jordi Cortadella and Lana Josipovic. 2023. Eliminating Excessive Dynamism of Dataflow Circuits Using Model Checking. In Proceedings of the 2023 ACM\/SIGDA International Symposium on Field Programmable Gate Arrays. https:\/\/doi.org\/10.1145\/3543622.3573196 10.1145\/3543622.3573196","DOI":"10.1145\/3543622.3573196"},{"key":"e_1_3_1_58_1","doi-asserted-by":"crossref","unstructured":"Ruifan Xu Youwei Xiao Jin Luo and Yun Liang. 2022. HECTOR: A Multi-level Intermediate Representation for Hardware Synthesis Methodologies. In International Conference On Computer Aided Design (ICCAD). https:\/\/doi.org\/10.1145\/3508352.3549370 10.1145\/3508352.3549370","DOI":"10.1145\/3508352.3549370"},{"key":"e_1_3_1_59_1","doi-asserted-by":"crossref","unstructured":"Zhenya Zang Uwe Dolinsky Pietro Ghiglio Stefano Cherubin Mehdi Goli and Shufan Yang. 2023. Building a Reusable and Extensible Automatic Compiler Infrastructure for Reconfigurable Devices. https:\/\/doi.org\/10.1109\/FPL60245.2023.00062 10.1109\/FPL60245.2023.00062","DOI":"10.1109\/FPL60245.2023.00062"},{"key":"e_1_3_1_60_1","unstructured":"Zhiru Zhang Yiping Fan Wei Jiang Guoling Han Changqi Yang and Jason Cong. 2008. AutoPilot: A platform-based ESL synthesis system. In High-Level Synthesis."}],"container-title":["Proceedings of the ACM on Programming Languages"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3689790","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3689790","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,2,4]],"date-time":"2026-02-04T09:11:48Z","timestamp":1770196308000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3689790"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,10,8]]},"references-count":59,"journal-issue":{"issue":"OOPSLA2","published-print":{"date-parts":[[2024,10,8]]}},"alternative-id":["10.1145\/3689790"],"URL":"https:\/\/doi.org\/10.1145\/3689790","relation":{},"ISSN":["2475-1421"],"issn-type":[{"value":"2475-1421","type":"electronic"}],"subject":[],"published":{"date-parts":[[2024,10,8]]},"assertion":[{"value":"2024-04-05","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2024-08-18","order":2,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2024-10-08","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}