{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,21]],"date-time":"2025-08-21T16:48:00Z","timestamp":1755794880063,"version":"3.44.0"},"publisher-location":"New York, NY, USA","reference-count":60,"publisher":"ACM","license":[{"start":{"date-parts":[[2025,7,20]],"date-time":"2025-07-20T00:00:00Z","timestamp":1752969600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/https:\/\/doi.org\/10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["62276006"],"award-info":[{"award-number":["62276006"]}],"id":[{"id":"10.13039\/https:\/\/doi.org\/10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2025,7,20]]},"DOI":"10.1145\/3690624.3709185","type":"proceedings-article","created":{"date-parts":[[2025,4,4]],"date-time":"2025-04-04T18:44:43Z","timestamp":1743792283000},"page":"484-495","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["TransPlace: Transferable Circuit Global Placement via Graph Neural Network"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0009-0007-0291-8762","authenticated-orcid":false,"given":"Yunbo","family":"Hou","sequence":"first","affiliation":[{"name":"School of Software and Microelectronics, Peking University, Beijing, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8510-3716","authenticated-orcid":false,"given":"Haoran","family":"Ye","sequence":"additional","affiliation":[{"name":"The State Key Laboratory of General Artificial Intelligence, Peking University, Beijing, China, and School of Intelligence Science and Technology, Peking University, Beijing, China"}]},{"ORCID":"https:\/\/orcid.org\/0009-0008-1358-9594","authenticated-orcid":false,"given":"Shuwen","family":"Yang","sequence":"additional","affiliation":[{"name":"DP Technology, Beijing, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9871-4682","authenticated-orcid":false,"given":"Yingxue","family":"Zhang","sequence":"additional","affiliation":[{"name":"Huawei Noah's Ark Lab, Markham, Ontario, Canada"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6239-6774","authenticated-orcid":false,"given":"Siyuan","family":"Xu","sequence":"additional","affiliation":[{"name":"Huawei Noah's Ark Lab, Shenzhen, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8295-2520","authenticated-orcid":false,"given":"Guojie","family":"Song","sequence":"additional","affiliation":[{"name":"The State Key Laboratory of General Artificial Intelligence, Peking University, Beijing, China, and School of Intelligence Science and Technology, Peking University, Beijing, China"}]}],"member":"320","published-online":{"date-parts":[[2025,7,20]]},"reference":[{"key":"e_1_3_2_2_1_1","first-page":"12","article-title":"Multilevel Dataflow-Driven Macro Placement Guided by RTL Structure and Analytical Methods","volume":"40","author":"Alex Vidal-Obiols","year":"2021","unstructured":"Vidal-Obiols Alex, Cortadella Jordi, Petit Jordi, Galceran-Oms Marc, and Martorell Ferran. 2021. Multilevel Dataflow-Driven Macro Placement Guided by RTL Structure and Analytical Methods. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 40, 12 (Dec. 2021), 2542--2555.","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"e_1_3_2_2_2_1","volume-title":"What makes a design difficult to route. Paper presented at the 10th International Symposium on Physical Design","author":"Alpert Charles J.","year":"2010","unstructured":"Charles J. Alpert, Zhuo Li, Michael D. Moffitt, Gi-Joon Nam, Jarrod A. Roy, and Gustavo Tellez. 2010. What makes a design difficult to route. Paper presented at the 10th International Symposium on Physical Design, San Francisco, California, USA, 14-16 March 2010."},{"key":"e_1_3_2_2_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/3566097.3568345"},{"key":"e_1_3_2_2_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.736565"},{"key":"e_1_3_2_2_5_1","first-page":"7862","article-title":"A graph placement methodology for fast chip design","volume":"594","author":"Azalia Mirhoseini","year":"2021","unstructured":"Mirhoseini Azalia and Anna Goldie. 2021. A graph placement methodology for fast chip design. Nature, Vol. 594, 7862 (Jun. 2021), 207--212.","journal-title":"Nature"},{"key":"e_1_3_2_2_6_1","doi-asserted-by":"crossref","unstructured":"Federico Berto Chuanbo Hua Junyoung Park Laurin Luttmann Yining Ma Fanchen Bu Jiarui Wang Haoran Ye Minsu Kim Sanghyeok Choi Nayeli Gast Zepeda Andr\u00e9 Hottung Jianan Zhou Jieyi Bi Yu Hu Fei Liu Hyeonah Kim Jiwoo Son Haeyeon Kim Davide Angioni Wouter Kool Zhiguang Cao Jie Zhang Kijung Shin Cathy Wu Sungsoo Ahn Guojie Song Changhyun Kwon Lin Xie and Jinkyoo Park. 2024. RL4CO: an Extensive Reinforcement Learning for Combinatorial Optimization Benchmark. arXiv preprint arXiv:2306.17100 (2024). https:\/\/github.com\/ai4co\/rl4co.","DOI":"10.1145\/3711896.3737433"},{"key":"e_1_3_2_2_7_1","volume-title":"Proceedings of the 59th ACM\/IEEE Design Automation Conference (DAC '22)","author":"Bowen Wang","year":"2022","unstructured":"Wang Bowen, Shen Guibao, Li Dong, Hao Jianye, Liu Wulong, Huang Yu, Wu Hongzhong, Lin Yibo, Chen Guangyong, and Heng Pheng Ann. 2022. LHNN: lattice hypergraph neural network for VLSI congestion prediction. In Proceedings of the 59th ACM\/IEEE Design Automation Conference (DAC '22). Association for Computing Machinery, New York, NY, USA, 1297--1302."},{"key":"e_1_3_2_2_8_1","volume-title":"January","author":"Breuer Melvin A.","year":"1977","unstructured":"Melvin A. Breuer. 1977. A Class of Min-Cut Placement Algorithms. Paper presented at the Proceedings of the 14th Design Automation Conference, January 1977."},{"key":"e_1_3_2_2_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/2717764.2723572"},{"key":"e_1_3_2_2_10_1","doi-asserted-by":"publisher","unstructured":"Fu-Chieh Chang Yu-Wei Tseng Ya-Wen Yu and Ssu-Rui Lee. 2022. Flexible Multiple-Objective Reinforcement Learning for Chip Placement. https:\/\/doi.org\/10.48550\/ARXIV.2204.06407","DOI":"10.48550\/ARXIV.2204.06407"},{"key":"e_1_3_2_2_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2778058"},{"key":"e_1_3_2_2_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.923063"},{"key":"e_1_3_2_2_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2859220"},{"key":"e_1_3_2_2_14_1","first-page":"26350","article-title":"The policy-gradient placement and generative routing neural networks for chip design","volume":"35","author":"Cheng Ruoyu","year":"2022","unstructured":"Ruoyu Cheng, Xianglong Lyu, Yang Li, Junjie Ye, Jianye Hao, and Junchi Yan. 2022. The policy-gradient placement and generative routing neural networks for chip design. Advances in Neural Information Processing Systems, Vol. 35 (2022), 26350--26362.","journal-title":"Advances in Neural Information Processing Systems"},{"key":"e_1_3_2_2_15_1","first-page":"16508","article-title":"On joint learning for solving placement and routing in chip design","volume":"34","author":"Cheng Ruoyu","year":"2021","unstructured":"Ruoyu Cheng and Junchi Yan. 2021. On joint learning for solving placement and routing in chip design. Advances in Neural Information Processing Systems, Vol. 34 (2021), 16508--16519.","journal-title":"Advances in Neural Information Processing Systems"},{"key":"e_1_3_2_2_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2102780"},{"key":"e_1_3_2_2_17_1","volume-title":"ICML","volume":"162","author":"Zhang He","year":"2022","unstructured":"weitao du, He Zhang, Yuanqi Du, Qi Meng, Wei Chen, Tie-Yan Liu, Nanning Zheng, and Bin Shao. 2022. SE(3) Equivariant Graph Neural Networks with Complete Local Frames. In ICML 2022, Vol. 162. Microsoft, PMLR, Honolulu, Hawaii, USA, 5583--5608."},{"key":"e_1_3_2_2_18_1","unstructured":"Yunbo Hou Haoran Ye Yingxue Zhang Siyuan Xu and Guojie Song. 2024. RoutePlacer: An End-to-End Routability-Aware Placer with Graph Neural Network. arxiv: 2406.02651 [cs.LG] https:\/\/arxiv.org\/abs\/2406.02651"},{"key":"e_1_3_2_2_19_1","volume-title":"USA","author":"Hsu Meng-Kai","year":"2011","unstructured":"Meng-Kai Hsu, Yao-Wen Chang, and Valeriy Balabanov. 2011. TSV-aware analytical placement for 3D IC designs. Paper presented at the 48th ACM\/EDAC\/IEEE Design Automation Conference, San Diego, CA, USA, 5-9 June 2011."},{"key":"e_1_3_2_2_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2014.2360453"},{"key":"e_1_3_2_2_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/MLCAD52597.2021.9531313"},{"key":"e_1_3_2_2_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/2699873"},{"key":"e_1_3_2_2_23_1","volume-title":"International Conference on Machine Learning. PMLR, JMLR.org","author":"Kim Haeyeon","year":"2023","unstructured":"Haeyeon Kim, Minsu Kim, Federico Berto, Joungho Kim, and Jinkyoo Park. 2023. Devformer: A symmetric transformer for context-aware device placement. In International Conference on Machine Learning. PMLR, JMLR.org, Honolulu, Hawaii, USA, 16541--16566."},{"key":"e_1_3_2_2_24_1","doi-asserted-by":"publisher","DOI":"10.5555\/2840819.2840949"},{"key":"e_1_3_2_2_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-SoC.2019.8920342"},{"key":"e_1_3_2_2_26_1","doi-asserted-by":"publisher","DOI":"10.1063\/1.5019779"},{"key":"e_1_3_2_2_27_1","doi-asserted-by":"publisher","DOI":"10.5555\/3618408.3619165"},{"key":"e_1_3_2_2_28_1","first-page":"24019","article-title":"Maskplace: Fast chip placement via reinforced visual representation learning","volume":"35","author":"Lai Yao","year":"2022","unstructured":"Yao Lai, Yao Mu, and Ping Luo. 2022. Maskplace: Fast chip placement via reinforced visual representation learning. Advances in Neural Information Processing Systems, Vol. 35 (2022), 24019--24030.","journal-title":"Advances in Neural Information Processing Systems"},{"key":"e_1_3_2_2_29_1","doi-asserted-by":"publisher","DOI":"10.23919\/DATE54114.2022.9774725"},{"key":"e_1_3_2_2_30_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2021.3057921"},{"key":"e_1_3_2_2_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2020.3003843"},{"key":"e_1_3_2_2_32_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2020.2971531"},{"key":"e_1_3_2_2_33_1","doi-asserted-by":"publisher","DOI":"10.1109\/CSTIC49141.2020.9282573"},{"key":"e_1_3_2_2_34_1","volume-title":"Automation & Test in Europe Conference & Exhibition (DATE). IEEE Press","author":"Lin Zhifeng","year":"2021","unstructured":"Zhifeng Lin, Yanyue Xie, Gang Qian, Jianli Chen, Sifei Wang, Jun Yu, and Yao-Wen Chang. 2021c. Timing-Driven Placement for FPGAs with Heterogeneous Architectures and Clock Constraints. In 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE Press, New York, NY, USA, 1564--1569."},{"key":"e_1_3_2_2_35_1","volume-title":"ISPD 2019 Initial Detailed Routing Contest and Benchmark with Advanced Routing Rules. Paper presented at the Proceedings of the 2019 Symposium on International Symposium on Physical Design","author":"Liu Wen-Hao","year":"2019","unstructured":"Wen-Hao Liu, Stefanus Mantik, Wing-Kai Chow, Yixiao Ding, Amin Farshidi, and Gracieli Posser. 2019b. ISPD 2019 Initial Detailed Routing Contest and Benchmark with Advanced Routing Rules. Paper presented at the Proceedings of the 2019 Symposium on International Symposium on Physical Design, San Francisco, CA, USA, 14-17 April 2019."},{"key":"e_1_3_2_2_36_1","doi-asserted-by":"publisher","DOI":"10.1145\/3489517.3530484"},{"key":"e_1_3_2_2_37_1","first-page":"1","article-title":"Graphplanner: Floorplanning with graph neural network","volume":"28","author":"Liu Yiting","year":"2022","unstructured":"Yiting Liu, Ziyi Ju, Zhengming Li, Mingzhi Dong, Hai Zhou, Jia Wang, Fan Yang, Xuan Zeng, and Li Shang. 2022b. Graphplanner: Floorplanning with graph neural network. ACM Transactions on Design Automation of Electronic Systems, Vol. 28, 2 (2022), 1--24.","journal-title":"ACM Transactions on Design Automation of Electronic Systems"},{"key":"e_1_3_2_2_38_1","doi-asserted-by":"publisher","DOI":"10.1145\/3287624.3287677"},{"key":"e_1_3_2_2_39_1","doi-asserted-by":"publisher","DOI":"10.1145\/3508352.3561095"},{"key":"e_1_3_2_2_40_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD51958.2021.9643435"},{"key":"e_1_3_2_2_41_1","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18074.2021.9586138"},{"key":"e_1_3_2_2_42_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2021.3053191"},{"key":"e_1_3_2_2_43_1","doi-asserted-by":"publisher","DOI":"10.48550\/arXiv.2111.00234"},{"key":"e_1_3_2_2_44_1","volume-title":"International conference on machine learning. PMLR, Proceedings of Machine Learning Research, Virtual Event, 9323--9332","author":"Satorras Victor Garcia","year":"2021","unstructured":"Victor Garcia Satorras, Emiel Hoogeboom, and Max Welling. 2021. E (n) equivariant graph neural networks. In International conference on machine learning. PMLR, Proceedings of Machine Learning Research, Virtual Event, 9323--9332."},{"key":"e_1_3_2_2_45_1","doi-asserted-by":"publisher","DOI":"10.1145\/3529090"},{"key":"e_1_3_2_2_46_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1985.1052337"},{"key":"e_1_3_2_2_47_1","volume-title":"Advances in Neural Information Processing Systems","volume":"36","author":"Shi Yunqi","year":"2024","unstructured":"Yunqi Shi, Ke Xue, Song Lei, and Chao Qian. 2024. Macro placement by wire-mask-guided black-box optimization. Advances in Neural Information Processing Systems, Vol. 36 (2024), 19 pages."},{"key":"e_1_3_2_2_48_1","doi-asserted-by":"publisher","DOI":"10.48550\/arXiv.2306.16844"},{"key":"e_1_3_2_2_49_1","volume-title":"Portland","author":"Spindler Peter","year":"2008","unstructured":"Peter Spindler, Ulf Schlichtmann, and Frank M. Johannes. 2008. Abacus: Fast Legalization of Standard Cell Circuits with Minimal Movement. Paper presented at the Proceedings of the 2008 International Symposium on Physical Design, Portland, Oregon, USA, 13-16 April 2008."},{"key":"e_1_3_2_2_50_1","volume-title":"ISPD 2019 Initial Detailed Routing Contest and Benchmark with Advanced Routing Rules. Paper presented at the Proceedings of the 49th Annual Design Automation Conference","author":"Viswanathan Natarajan","year":"2012","unstructured":"Natarajan Viswanathan, Charles Alpert, Cliff Sze, Zhuo Li, and Yaoguang Wei. 2012. ISPD 2019 Initial Detailed Routing Contest and Benchmark with Advanced Routing Rules. Paper presented at the Proceedings of the 49th Annual Design Automation Conference, San Francisco, CA, USA, 3-7 June 2012."},{"key":"e_1_3_2_2_51_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.858348"},{"key":"e_1_3_2_2_52_1","doi-asserted-by":"publisher","DOI":"10.1145\/3453688.3461495"},{"key":"e_1_3_2_2_53_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNNLS.2020.2978386"},{"key":"e_1_3_2_2_54_1","volume-title":"Yokohama","author":"Xu Yue","year":"2009","unstructured":"Yue Xu, Yanheng Zhang, and Chris Chu. 2009. FastRoute 4.0: Global router with efficient via minimization. Paper presented at the 2009 Asia and South Pacific Design Automation Conference, Yokohama, 19-22 January 2009."},{"key":"e_1_3_2_2_55_1","volume-title":"Deep Molecular Representation Learning via Fusing Physical and Chemical Information. Paper presented at the Advances in Neural Information Processing Systems, 28 November -","author":"Yang Shuwen","year":"2022","unstructured":"Shuwen Yang, Ziyao Li, Guojie Song, and Lingsheng Cai. 2021. Deep Molecular Representation Learning via Fusing Physical and Chemical Information. Paper presented at the Advances in Neural Information Processing Systems, 28 November - 9 December 2022."},{"key":"e_1_3_2_2_56_1","unstructured":"Shuwen Yang Zhihao Yang Dong Li Yingxue Zhang Zhanguang Zhang Guojie Song and Jianye HAO. 2022. Versatile Multi-stage Graph Neural Network for Circuit Representation. In Advances in Neural Information Processing Systems Alice H. Oh Alekh Agarwal Danielle Belgrave and Kyunghyun Cho (Eds.). Curran Associates Inc. New Orleans Louisiana USA Article 1477 11 pages."},{"key":"e_1_3_2_2_57_1","unstructured":"Haoran Ye Jiarui Wang Zhiguang Cao Federico Berto Chuanbo Hua Haeyeon Kim Jinkyoo Park and Guojie Song. 2024. ReEvo: Large Language Models as Hyper-Heuristics with Reflective Evolution. In Advances in Neural Information Processing Systems. https:\/\/github.com\/ai4co\/reevo."},{"key":"e_1_3_2_2_58_1","volume-title":"USA","author":"Ye Haoran","year":"2023","unstructured":"Haoran Ye, Jiarui Wang, Zhiguang Cao, Helan Liang, and Yong Li. 2023. DeepACO: Neural-enhanced Ant Systems for Combinatorial Optimization. Paper presented at the Advances in Neural Information Processing Systems, New Orleans, USA, 10-16 December 2023."},{"key":"e_1_3_2_2_59_1","volume-title":"Singapore","author":"Zebulum Ricardo Salem","year":"2015","unstructured":"Ricardo Salem Zebulum, Marco Aur\u00e9lio Pacheco, and Marley Vellasco. 2015. A multi-objective optimisation methodology applied to the synthesis of low-power operational amplifiers. Paper presented at the 13th International Conference in Microelectronics and Packaging, Singapore, 7-9 December 2011."},{"key":"e_1_3_2_2_60_1","doi-asserted-by":"publisher","DOI":"10.1145\/3508352.3549361"}],"event":{"name":"KDD '25: The 31st ACM SIGKDD Conference on Knowledge Discovery and Data Mining","sponsor":["SIGMOD ACM Special Interest Group on Management of Data","SIGKDD ACM Special Interest Group on Knowledge Discovery in Data"],"location":"Toronto ON Canada","acronym":"KDD '25"},"container-title":["Proceedings of the 31st ACM SIGKDD Conference on Knowledge Discovery and Data Mining V.1"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3690624.3709185","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3690624.3709185","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,16]],"date-time":"2025-08-16T15:47:29Z","timestamp":1755359249000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3690624.3709185"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,7,20]]},"references-count":60,"alternative-id":["10.1145\/3690624.3709185","10.1145\/3690624"],"URL":"https:\/\/doi.org\/10.1145\/3690624.3709185","relation":{},"subject":[],"published":{"date-parts":[[2025,7,20]]},"assertion":[{"value":"2025-07-20","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}