{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,6]],"date-time":"2025-12-06T17:19:59Z","timestamp":1765041599855,"version":"3.44.0"},"reference-count":50,"publisher":"Association for Computing Machinery (ACM)","issue":"5","content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2025,9,30]]},"abstract":"<jats:p>\n            By harnessing fundamental quantum properties, a large-scale quantum computer could undermine currently deployed public-key algorithms. The post-quantum, code-based cryptosystem Classic McEliece (CM) addresses this security concern. However, its large public key size (up to 1.3 MB) poses various hardware implementation challenges. In this article, we focus on the high memory bandwidth requirements of the CM encoding function, in the context of heterogeneous CPU-FPGA devices. More concretely, we target the acceleration of public-key loading and processing from any globally shared or accelerator-private memory system. We present a novel and constant-time accelerator\n            <jats:monospace>eEnc<\/jats:monospace>\n            that exploits the elevated parallelization potential of FPGA devices to yield high-performance results. Our accelerator implements the encoding and the random error vector generation functions, which comprise the main computational load of Encapsulation. Two accelerator design variants are introduced, providing different hardware tradeoffs. Regarding intra-accelerator data communication, and unlike other state-of-the-art (SOTA) works, we combine a streaming protocol with task-level parallelization to remove the need to store the public key in accelerator-private memories. Our proposed design shows new record execution times over its SOTA counterparts, ranging on average from 3.5\u00d7 up to 7.7\u00d7 across the five security level parameter sets. Our end-to-end implementation in a Zynq SoC shows an average speedup of 2.2\u00d7 compared to a 64-bit vectorized CM software-baseline. The elevated logic resource consumption, characteristic of HLS designs, can be readily adjusted with a performance tradeoff.\n          <\/jats:p>","DOI":"10.1145\/3698395","type":"journal-article","created":{"date-parts":[[2024,10,2]],"date-time":"2024-10-02T05:12:21Z","timestamp":1727845941000},"page":"1-27","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["Leveraging HLS to Design a Versatile &amp; High-Performance Classic McEliece Accelerator"],"prefix":"10.1145","volume":"24","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-1912-5092","authenticated-orcid":false,"given":"Ioannis-Vatistas","family":"Kostalabros","sequence":"first","affiliation":[{"name":"Computer Architecture, Barcelona Supercomputing Center","place":["Barcelona, Spain"]}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6329-7380","authenticated-orcid":false,"given":"Jordi","family":"Ribes","sequence":"additional","affiliation":[{"name":"Enginyeria Inform\u00e0tica i Matem\u00e0tiques, Universitat Rovira i Virgili","place":["Tarragona, Spain"]}]},{"ORCID":"https:\/\/orcid.org\/0009-0008-8392-7579","authenticated-orcid":false,"given":"Xavier","family":"Carril","sequence":"additional","affiliation":[{"name":"Computer Architecture, Barcelona Supercomputing Center","place":["Barcelona, Spain"]}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7495-5980","authenticated-orcid":false,"given":"Oriol","family":"Farras","sequence":"additional","affiliation":[{"name":"Enginyeria Inform\u00e0tica i Matem\u00e0tiques, Universitat Rovira i Virgili","place":["Tarragona, Spain"]}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5393-3195","authenticated-orcid":false,"given":"Carles","family":"Hernandez","sequence":"additional","affiliation":[{"name":"Inform\u00e1tica de Sistemas y Computadores, Universitat Politecnica de Valencia","place":["Valencia, Spain"]}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9848-8758","authenticated-orcid":false,"given":"Miquel","family":"Moreto","sequence":"additional","affiliation":[{"name":"Computer Architecture, Barcelona Supercomputing Center","place":["Barcelona, Spain"]}]}],"member":"320","published-online":{"date-parts":[[2025,9,12]]},"reference":[{"key":"e_1_3_1_2_2","first-page":"73","volume-title":"Proceedings of the IEEE 38th International Conference on Computer Design (ICCD\u201920)","author":"Agrawal Rashmi","year":"2020","unstructured":"Rashmi Agrawal, Lake Bu, and Michel A Kinsy. 2020. Quantum-proof lightweight McEliece cryptosystem co-processor design. In Proceedings of the IEEE 38th International Conference on Computer Design (ICCD\u201920). IEEE, 73\u201379."},{"key":"e_1_3_1_3_2","unstructured":"Martin R. Albrecht Daniel J. Bernstein Tung Chou Carlos Cid Jan Gilcher Tanja Lange Varun Maram Ingo von Maurich Rafale Misoczki Ruben Niederhangen Kenneth G. Paterson Edoardo Perischetti Christiane Peters Peter Schwabe Nicolas Sendrier Jakub Szefer Can Jung Tjhai Martin Tomlinson and Wen Wang. 2020. Classic McEliece: Conservative code-based cryptography. NIST PQC call Supporting Documentation of the Round-3 Submission."},{"key":"e_1_3_1_4_2","unstructured":"Martin R. Albrecht Daniel J. Bernstein Tung Chou Carlos Cid Jan Gilcher Tanja Lange Varun Maram Ingo von Maurich Rafale Misoczki Ruben Niederhangen Kenneth G. Paterson Edoardo Perischetti Christiane Peters Peter Schwabe Nicolas Sendrier Jakub Szefer Can Jung Tjhai Martin Tomlinson and Wen Wang. 2022. Classic McEliece: Conservative code-based cryptography. NIST PQC call Supporting Documentation of the Round-4 Submission."},{"key":"e_1_3_1_5_2","unstructured":"Martin R. Albrecht Daniel J. Bernstein Tung Chou Carlos Cid Jan Gilcher Tanja Lange Varun Maram Ingo von Maurich Rafale Misoczki Ruben Niederhangen Kenneth G. Paterson Edoardo Perischetti Christiane Peters Peter Schwabe Nicolas Sendrier Jakub Szefer Can Jung Tjhai Martin Tomlinson and Wen Wang. Oct 2022. Classic McEliece: Source Code of Round 4 NIST Submission. Retrieved from https:\/\/classic.mceliece.org\/nist\/mceliece-20221023.tar.gz"},{"key":"e_1_3_1_6_2","doi-asserted-by":"publisher","DOI":"10.3390\/app13020757"},{"key":"e_1_3_1_7_2","article-title":"NIST post-quantum cryptography\u2014A hardware evaluation study.","author":"Basu Kanad","year":"2019","unstructured":"Kanad Basu, Deepraj Soni, Mohammed Nabeel, and Ramesh Karri. 2019. NIST post-quantum cryptography\u2014A hardware evaluation study. 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