{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,24]],"date-time":"2026-04-24T02:03:00Z","timestamp":1776996180643,"version":"3.51.4"},"publisher-location":"New York, NY, USA","reference-count":51,"publisher":"ACM","license":[{"start":{"date-parts":[[2025,2,27]],"date-time":"2025-02-27T00:00:00Z","timestamp":1740614400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"DOI":"10.13039\/501100006374","name":"National Key Research and Development Program of China","doi-asserted-by":"publisher","award":["2023YFB4405105"],"award-info":[{"award-number":["2023YFB4405105"]}],"id":[{"id":"10.13039\/501100006374","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100006374","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["62090023"],"award-info":[{"award-number":["62090023"]}],"id":[{"id":"10.13039\/501100006374","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2025,2,27]]},"DOI":"10.1145\/3706628.3708872","type":"proceedings-article","created":{"date-parts":[[2025,2,26]],"date-time":"2025-02-26T12:22:11Z","timestamp":1740572531000},"page":"199-210","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["Latency Insensitivity Testing for Dataflow HLS Designs"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-2791-2555","authenticated-orcid":false,"given":"Jianyi","family":"Cheng","sequence":"first","affiliation":[{"name":"School of Informatics, The University of Edinburgh, Edinburgh, United Kingdom"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0007-6426-0708","authenticated-orcid":false,"given":"Lianghui","family":"Wang","sequence":"additional","affiliation":[{"name":"Institute of Computing Technology, Chinese Academy of Sciences & University of Science and Technology of China, Beijing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0007-4600-1331","authenticated-orcid":false,"given":"Zijian","family":"Jiang","sequence":"additional","affiliation":[{"name":"State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences & University of Chinese Academy of Sciences, Beijing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6565-5276","authenticated-orcid":false,"given":"Yungang","family":"Bao","sequence":"additional","affiliation":[{"name":"State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences & University of Chinese Academy of Sciences, Beijing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8461-0820","authenticated-orcid":false,"given":"Kan","family":"Shi","sequence":"additional","affiliation":[{"name":"State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences & University of Chinese Academy of Sciences, Beijing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2025,2,27]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"2024. AMD Xilinx Vitis HLS. https:\/\/www.xilinx.com\/products\/design-tools\/vitis\/vitis-hls.html"},{"key":"e_1_3_2_1_2_1","unstructured":"2024. AMD Xilinx Vivado. https:\/\/www.xilinx.com\/products\/design-tools\/vivado.html"},{"key":"e_1_3_2_1_3_1","unstructured":"2024. Cadence Stratus HLS. https:\/\/www.cadence.com\/en_US\/home\/tools\/digitaldesign- and-signoff\/synthesis\/stratus-high-level-synthesis.html"},{"key":"e_1_3_2_1_4_1","unstructured":"2024. ModelSim HDL simulator. https:\/\/eda.sw.siemens.com\/en-US\/ic\/modelsim\/"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2021.3090339"},{"key":"e_1_3_2_1_6_1","unstructured":"AMD. 2024. ChipScope Integrated Logic Analyzer (ILA). https:\/\/www.xilinx. com\/products\/intellectual-property\/chipscope_ila.html"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/3373087.3375307"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.640619"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228584"},{"key":"e_1_3_2_1_10_1","volume-title":"Proceedings","author":"Beece Daniel K","year":"1988","unstructured":"Daniel K Beece, G Deiberg, Georgina Papp, and Frank Villante. 1988. The IBM engineering verification engine. In 25th ACM\/IEEE, Design Automation Conference. Proceedings 1988. IEEE, 218--224."},{"key":"e_1_3_2_1_11_1","volume-title":"ATHEENA: A Toolflow for Hardware Early-Exit Network Automation. In 2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE, 121--132","author":"Biggs Benjamin","year":"2023","unstructured":"Benjamin Biggs, Christos-Savvas Bouganis, and George Constantinides. 2023. ATHEENA: A Toolflow for Hardware Early-Exit Network Automation. In 2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE, 121--132."},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/3385412.3385965"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/3240765.3240850"},{"key":"e_1_3_2_1_14_1","volume-title":"2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE, 204--213","author":"Chi Yuze","year":"2021","unstructured":"Yuze Chi, Licheng Guo, Jason Lau, Young-kyu Choi, Jie Wang, and Jason Cong. 2021. Extending high-level synthesis for task-parallel programs. In 2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE, 204--213."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2020.2970597"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/3240765.3240838"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/3385412.3385983"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/3626202.3637556"},{"key":"e_1_3_2_1_19_1","volume-title":"Accelerating RTL Simulation with Hardware-Software Co-Design. In Symposium on Microarchitecture (MICRO'23)","author":"Elsabbagh Fares","year":"2023","unstructured":"Fares Elsabbagh, Shabnam Sheikhha, Victor A Ying, QuanMNguyen, Joel S Emer, and Daniel Sanchez. 2023. Accelerating RTL Simulation with Hardware-Software Co-Design. In Symposium on Microarchitecture (MICRO'23)."},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/3609335"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICAIS50930.2021.9396034"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/3485494"},{"key":"e_1_3_2_1_23_1","volume-title":"Formal co-validation of low-level hardware\/- software interfaces. In 2013 Formal Methods in Computer-Aided Design","author":"Horn Alex","unstructured":"Alex Horn, Michael Tautschnig, Celina Val, Lihao Liang, Tom Melham, Jim Grundy, and Daniel Kroening. 2013. Formal co-validation of low-level hardware\/- software interfaces. In 2013 Formal Methods in Computer-Aided Design. IEEE, 121--128."},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2021.3123465"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICM48031.2019.9021657"},{"key":"e_1_3_2_1_26_1","unstructured":"Intel. 2024. High-Level Synthesis Compiler. https:\/\/www.intel.com\/content\/www\/us\/en\/software\/programmable\/quartus-prime\/hls-compiler.html"},{"key":"e_1_3_2_1_27_1","unstructured":"Intel. 2024. Signal Tap Logic Analyzer: Introduction & Getting Started. https:\/\/ www.intel.com\/content\/www\/us\/en\/docs\/programmable\/683819\/23--3\/faq.html"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/3174243.3174264"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00014"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1109\/ASIC.1993.410733"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/3192366.3192379"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-44614-1_8"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/3582016.3582019"},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1145\/3289602.3293910"},{"key":"e_1_3_2_1_35_1","volume-title":"The BSD conference","volume":"5","author":"Lattner Chris","year":"2008","unstructured":"Chris Lattner. 2008. LLVM and Clang: Next generation compiler technology. In The BSD conference, Vol. 5. 1--20."},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1109\/MEMCOD.2015.7340479"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1145\/3385412.3385974"},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1145\/3591234"},{"key":"e_1_3_2_1_39_1","unstructured":"Non-Blocking API in Vitis HLS. 2024. https:\/\/docs.amd.com\/r\/en-US\/ug1399-vitis-hls\/Non-Blocking-API"},{"key":"e_1_3_2_1_40_1","volume-title":"19th Design Automation Conference. IEEE, 51--54","author":"Pfister Gregory F","year":"1982","unstructured":"Gregory F Pfister. 1982. The yorktown simulation engine: Introduction. In 19th Design Automation Conference. IEEE, 51--54."},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1145\/3445814.3446720"},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM57271.2023.00010"},{"key":"e_1_3_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1145\/3297858.3304010"},{"key":"e_1_3_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1145\/3543622.3573187"},{"key":"e_1_3_2_1_45_1","volume-title":"Design Automation Conference.","author":"Snyder Wilson","year":"2004","unstructured":"Wilson Snyder. 2004. Verilator and systemperl. In North American SystemC Users' Group, Design Automation Conference."},{"key":"e_1_3_2_1_46_1","unstructured":"Synopsys HECTOR. 2024. https:\/\/www.synopsys.com\/verification\/static-andformal-verification\/vc-formal\/vc-formal-datapath-validation.html"},{"key":"e_1_3_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.1145\/1119772.1119930"},{"key":"e_1_3_2_1_48_1","volume-title":"The 2021 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays. 93--104","author":"Guo Licheng","year":"2021","unstructured":"JieWang, Licheng Guo, and Jason Cong. 2021. AutoSA: A polyhedral compiler for high-performance systolic arrays on FPGA. In The 2021 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays. 93--104."},{"key":"e_1_3_2_1_49_1","doi-asserted-by":"publisher","DOI":"10.5555\/513581.513584"},{"key":"e_1_3_2_1_50_1","doi-asserted-by":"publisher","DOI":"10.1145\/3490422.3502369"},{"key":"e_1_3_2_1_51_1","doi-asserted-by":"publisher","DOI":"10.1145\/3489517.3530603"}],"event":{"name":"FPGA '25: The 2025 ACM\/SIGDA International Symposium on Field Programmable Gate Arrays","location":"Monterey CA USA","acronym":"FPGA '25","sponsor":["SIGDA ACM Special Interest Group on Design Automation"]},"container-title":["Proceedings of the 2025 ACM\/SIGDA International Symposium on Field Programmable Gate Arrays"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3706628.3708872","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3706628.3708872","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,22]],"date-time":"2025-08-22T21:53:51Z","timestamp":1755899631000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3706628.3708872"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,2,27]]},"references-count":51,"alternative-id":["10.1145\/3706628.3708872","10.1145\/3706628"],"URL":"https:\/\/doi.org\/10.1145\/3706628.3708872","relation":{},"subject":[],"published":{"date-parts":[[2025,2,27]]},"assertion":[{"value":"2025-02-27","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}