{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,27]],"date-time":"2026-03-27T17:07:01Z","timestamp":1774631221746,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":18,"publisher":"ACM","license":[{"start":{"date-parts":[[2024,10,31]],"date-time":"2024-10-31T00:00:00Z","timestamp":1730332800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100006374","name":"China Scholarship Council","doi-asserted-by":"publisher","award":["202307650033"],"award-info":[{"award-number":["202307650033"]}],"id":[{"id":"10.13039\/501100006374","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2024,10,31]]},"DOI":"10.1145\/3708358.3709350","type":"proceedings-article","created":{"date-parts":[[2025,1,23]],"date-time":"2025-01-23T06:18:23Z","timestamp":1737613103000},"page":"1-8","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["The Influence of Interconnection Complexity on the FPGA CAD Flow"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0009-0003-8435-3478","authenticated-orcid":false,"given":"Xiaoke","family":"Wang","sequence":"first","affiliation":[{"name":"Department of Electronics and Information Systems, Hardware and Embedded Systems Group, Ghent University, Ghent, Belgium"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4477-5313","authenticated-orcid":false,"given":"Dirk","family":"Stroobandt","sequence":"additional","affiliation":[{"name":"Department of Electronics and Information Systems, Hardware and Embedded Systems Group, Ghent University, Ghent, Belgium"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2025,1,23]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2023.3272582"},{"key":"e_1_3_2_1_2_1","volume-title":"VPR: a new packing, placement and routing tool for FPGA research","author":"Betz Vaughn","unstructured":"Vaughn Betz and Jonathan Rose. 1997. VPR: a new packing, placement and routing tool for FPGA research. In Field-Programmable Logic and Applications, Wayne Luk, Peter Y. K. Cheung, and Manfred Glesner (Eds.). Springer Berlin Heidelberg, Berlin, Heidelberg, 213--222."},{"key":"e_1_3_2_1_3_1","volume-title":"A hypergraph partitioning package","author":"Karypis George","year":"1998","unstructured":"George Karypis and Vipin Kumar. 1998. A hypergraph partitioning package. Army HPC Research Center, Department of Computer Science & Engineering, University of Minnesota (1998)."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1971.223159"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/1508128.1508135"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.846364"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/3632409.3632838"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2020.2998435"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/3388617"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2013.6645503"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/605440.605448"},{"key":"e_1_3_2_1_12_1","volume-title":"A priori wire length estimates for digital design","author":"Stroobandt Dirk","unstructured":"Dirk Stroobandt. 2001. A priori wire length estimates for digital design. Springer Science & Business Media."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1016\/S0167-9260(99)00002-4"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/299996.300023"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.863641"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/3665283.3665300"},{"key":"e_1_3_2_1_17_1","unstructured":"Peter Verplaetse and Dirk Stroobandt. 2002. Gnl v1.1.2. https:\/\/users.elis.ugent.be\/~dstrooba\/gnl\/"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2000.858726"}],"event":{"name":"SLIP '24: 2024 ACM International Workshop on System-Level Interconnect Pathfinding","location":"Newark NJ USA","acronym":"SLIP '24","sponsor":["SIGDA ACM Special Interest Group on Design Automation"]},"container-title":["Proceedings of the 2024 ACM International Workshop on System-Level Interconnect Pathfinding"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3708358.3709350","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3708358.3709350","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,23]],"date-time":"2025-08-23T20:35:56Z","timestamp":1755981356000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3708358.3709350"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,10,31]]},"references-count":18,"alternative-id":["10.1145\/3708358.3709350","10.1145\/3708358"],"URL":"https:\/\/doi.org\/10.1145\/3708358.3709350","relation":{},"subject":[],"published":{"date-parts":[[2024,10,31]]},"assertion":[{"value":"2025-01-23","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}