{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,7]],"date-time":"2025-12-07T13:10:53Z","timestamp":1765113053231,"version":"3.43.0"},"publisher-location":"New York, NY, USA","reference-count":36,"publisher":"ACM","content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2025,8,25]]},"DOI":"10.1145\/3708821.3733891","type":"proceedings-article","created":{"date-parts":[[2025,8,13]],"date-time":"2025-08-13T06:30:56Z","timestamp":1755066656000},"page":"13-29","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["An Efficient Circuit Synthesis Framework for TFHE via Convex Sub-graph Optimization"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0009-0008-7731-4477","authenticated-orcid":false,"given":"Animesh","family":"Singh","sequence":"first","affiliation":[{"name":"Computer Science and Engineering, Indian Institute of Technology, Kharagpur, Kharagpur, West Bengal, India"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6368-0718","authenticated-orcid":false,"given":"Ayantika","family":"Chatterjee","sequence":"additional","affiliation":[{"name":"Advanced Technology Development Centre, Indian Institute of Technology, Kharagpur, Kharagpur, West Bengal, India"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8818-6983","authenticated-orcid":false,"given":"Anupam","family":"Chattopadhyay","sequence":"additional","affiliation":[{"name":"Computer Science and Engineering, Nanyang Technological University, Singapore, Singapore, Singapore"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6499-8346","authenticated-orcid":false,"given":"Debdeep","family":"Mukhopadhyay","sequence":"additional","affiliation":[{"name":"Computer Science and Engineering, Indian Institute of Technology, Kharagpur, Kharagpur, West Bengal, India"}]}],"member":"320","published-online":{"date-parts":[[2025,8,24]]},"reference":[{"key":"e_1_3_3_2_2_2","unstructured":"[n. d.]. KU Leuven COSIC. SCALE-MAMBA 2019. https:\/\/github.com\/ KULeuven-COSIC\/SCALE-MAMBA."},{"key":"e_1_3_3_2_3_2","doi-asserted-by":"crossref","unstructured":"Martin\u00a0R Albrecht Rachel Player and Sam Scott. 2015. On the concrete hardness of learning with errors. Journal of Mathematical Cryptology 9 3 (2015) 169\u2013203.","DOI":"10.1515\/jmc-2015-0016"},{"key":"e_1_3_3_2_4_2","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-40186-3_17"},{"key":"e_1_3_3_2_5_2","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-32009-5_50"},{"key":"e_1_3_3_2_6_2","unstructured":"Sergiu Carpov. 2024. A fast heuristic for mapping Boolean circuits to functional bootstrapping. Cryptology ePrint Archive (2024)."},{"key":"e_1_3_3_2_7_2","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-12612-4_6"},{"key":"e_1_3_3_2_8_2","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-70694-8_14"},{"key":"e_1_3_3_2_9_2","doi-asserted-by":"crossref","unstructured":"Ilaria Chillotti Nicolas Gama Mariya Georgieva and Malika Izabach\u00e8ne. 2020. TFHE: fast fully homomorphic encryption over the torus. Journal of Cryptology 33 1 (2020) 34\u201391.","DOI":"10.1007\/s00145-019-09319-x"},{"key":"e_1_3_3_2_10_2","volume-title":"WAHC 2020-8th Workshop on Encrypted Computing & Applied Homomorphic Cryptography","author":"Chillotti Ilaria","year":"2020","unstructured":"Ilaria Chillotti, Marc Joye, Damien Ligier, Jean-Baptiste Orfila, and Samuel Tap. 2020. Concrete: Concrete operates on ciphertexts rapidly by extending tfhe. In WAHC 2020-8th Workshop on Encrypted Computing & Applied Homomorphic Cryptography."},{"key":"e_1_3_3_2_11_2","doi-asserted-by":"publisher","DOI":"10.1145\/2810103.2813678"},{"key":"e_1_3_3_2_12_2","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-662-46800-5_24"},{"key":"e_1_3_3_2_13_2","doi-asserted-by":"publisher","DOI":"10.1145\/1536414.1536440"},{"key":"e_1_3_3_2_14_2","unstructured":"Zahra Ghodsi Akshaj\u00a0Kumar Veldanda Brandon Reagen and Siddharth Garg. 2020. Cryptonas: Private inference on a relu budget. Advances in Neural Information Processing Systems 33 (2020) 16961\u201316971."},{"key":"e_1_3_3_2_15_2","unstructured":"Shruthi Gorantala Rob Springer Sean Purser-Haskell William Lam Royce Wilson Asra Ali Eric\u00a0P Astor Itai Zukerman Sam Ruth Christoph Dibak et\u00a0al. 2021. A general purpose transpiler for fully homomorphic encryption. arXiv preprint arXiv:https:\/\/arXiv.org\/abs\/2106.07893 (2021)."},{"key":"e_1_3_3_2_16_2","unstructured":"Charles Gouert Vinu Joseph Steven Dalton Cedric Augonnet Michael Garland and Nektarios\u00a0Georgios Tsoutsos. 2023. Accelerated Encrypted Execution of General-Purpose Applications. IACR Cryptol. ePrint Arch. 2023 (2023) 641."},{"key":"e_1_3_3_2_17_2","doi-asserted-by":"crossref","unstructured":"Charles Gouert Dimitris Mouris and Nektarios\u00a0Georgios Tsoutsos. 2023. Helm: Navigating homomorphic encryption through gates and lookup tables. Cryptology ePrint Archive (2023).","DOI":"10.56553\/popets-2023-0075"},{"key":"e_1_3_3_2_18_2","doi-asserted-by":"crossref","unstructured":"Zhenyu Guan Ran Mao Qianyun Zhang Zhou Zhang Zian Zhao and Song Bian. 2024. Autohog: Automating homomorphic gate design for large-scale logic circuit evaluation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 43 7 (2024) 1971\u20131983.","DOI":"10.1109\/TCAD.2024.3357598"},{"key":"e_1_3_3_2_19_2","doi-asserted-by":"publisher","DOI":"10.1109\/SP.2019.00028"},{"key":"e_1_3_3_2_20_2","unstructured":"Xiao Hu Zhihao Li Zhongfeng Wang and Xianhui Lu. 2024. ALT: Area-Efficient and Low-Latency FPGA Design for Torus Fully Homomorphic Encryption. IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2024)."},{"key":"e_1_3_3_2_21_2","doi-asserted-by":"publisher","DOI":"10.1145\/3489517.3530435"},{"key":"e_1_3_3_2_22_2","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-13190-5_1"},{"key":"e_1_3_3_2_23_2","first-page":"4007","volume-title":"30th USENIX security symposium (USENIX Security 21)","author":"Matsuoka Kotaro","year":"2021","unstructured":"Kotaro Matsuoka, Ryotaro Banno, Naoki Matsumoto, Takashi Sato, and Song Bian. 2021. Virtual secure platform: A { Five-Stage} pipeline processor over { TFHE}. In 30th USENIX security symposium (USENIX Security 21). 4007\u20134024."},{"key":"e_1_3_3_2_24_2","doi-asserted-by":"publisher","DOI":"10.1145\/3474366.3486927"},{"key":"e_1_3_3_2_25_2","doi-asserted-by":"crossref","unstructured":"Johannes Mono Kamil Kluczniak and Tim G\u00fcneysu. 2024. Improved Circuit Synthesis with Multi-Value Bootstrapping for FHEW-like Schemes. IACR Transactions on Cryptographic Hardware and Embedded Systems 2024 4 (2024) 633\u2013656.","DOI":"10.46586\/tches.v2024.i4.633-656"},{"key":"e_1_3_3_2_26_2","doi-asserted-by":"crossref","unstructured":"Joseph Reddington and Kubilay Atasu. 2011. Complexity of computing convex subgraphs in custom instruction synthesis. IEEE transactions on very large scale integration (VLSI) systems 20 12 (2011) 2337\u20132341.","DOI":"10.1109\/TVLSI.2011.2173221"},{"key":"e_1_3_3_2_27_2","doi-asserted-by":"crossref","unstructured":"Oded Regev. 2009. On lattices learning with errors random linear codes and cryptography. Journal of the ACM (JACM) 56 6 (2009) 1\u201340.","DOI":"10.1145\/1568318.1568324"},{"key":"e_1_3_3_2_28_2","doi-asserted-by":"crossref","unstructured":"Animesh Singh Smita Das Anirban Chakraborty Rajat Sadhukhan Ayantika Chatterjee and Debdeep Mukhopadhyay. 2023. FHEDA: Efficient Circuit Synthesis with Reduced Bootstrapping for Torus FHE. Cryptology ePrint Archive (2023).","DOI":"10.1109\/EuroSP60621.2024.00052"},{"key":"e_1_3_3_2_29_2","doi-asserted-by":"publisher","DOI":"10.1109\/SP.2015.32"},{"key":"e_1_3_3_2_30_2","unstructured":"Roy Stracovsky Rasoul\u00a0Akhavan Mahdavi and Florian Kerschbaum. 2022. Faster evaluation of AES using TFHE. Poster Session FHE. Org (2022)."},{"key":"e_1_3_3_2_31_2","doi-asserted-by":"publisher","DOI":"10.1145\/3605759.3625260"},{"key":"e_1_3_3_2_32_2","doi-asserted-by":"crossref","unstructured":"Furkan Turan Sujoy\u00a0Sinha Roy and Ingrid Verbauwhede. 2020. HEAWS: An accelerator for homomorphic encryption on the Amazon AWS FPGA. IEEE Trans. Comput. 69 8 (2020) 1185\u20131196.","DOI":"10.1109\/TC.2020.2988765"},{"key":"e_1_3_3_2_33_2","doi-asserted-by":"publisher","DOI":"10.1145\/3576915.3623159"},{"key":"e_1_3_3_2_34_2","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-031-58723-8_12"},{"key":"e_1_3_3_2_35_2","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-031-49187-0_20"},{"key":"e_1_3_3_2_36_2","unstructured":"Clifford Wolf. 2016. Yosys open synthesis suite. (2016)."},{"key":"e_1_3_3_2_37_2","doi-asserted-by":"publisher","DOI":"10.1145\/3689945.3694803"}],"event":{"name":"ASIA CCS '25: 20th ACM Asia Conference on Computer and Communications Security","location":"Hanoi Vietnam","acronym":"ASIA CCS '25","sponsor":["SIGSAC ACM Special Interest Group on Security, Audit, and Control"]},"container-title":["Proceedings of the 20th ACM Asia Conference on Computer and Communications Security"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3708821.3733891","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,13]],"date-time":"2025-08-13T07:27:30Z","timestamp":1755070050000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3708821.3733891"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,8,24]]},"references-count":36,"alternative-id":["10.1145\/3708821.3733891","10.1145\/3708821"],"URL":"https:\/\/doi.org\/10.1145\/3708821.3733891","relation":{},"subject":[],"published":{"date-parts":[[2025,8,24]]},"assertion":[{"value":"2025-08-24","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}