{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,24]],"date-time":"2025-08-24T00:03:31Z","timestamp":1755993811131,"version":"3.44.0"},"reference-count":36,"publisher":"Association for Computing Machinery (ACM)","issue":"1","license":[{"start":{"date-parts":[[2025,3,6]],"date-time":"2025-03-06T00:00:00Z","timestamp":1741219200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["Proc. ACM Meas. Anal. Comput. Syst."],"published-print":{"date-parts":[[2025,3,6]]},"abstract":"<jats:p>The exponential growth in demand for high-performance computing systems has created an urgent requirement for innovative memory technologies that can provide higher bandwidth and enhanced capacity scalability. In particular, Compute Express Link (CXL) has emerged as a promising solution for memory expansion and system acceleration. Hash-based index structures are widely recognized as fundamental components of in-memory database systems, and they are commonly used for indexing in-memory key-value stores due to their capability for rapid lookup performance. How to design and maintain a hash index structure in a CXLbased disaggregated memory system, with comprehensive consolidation, is a challenging topic of in-depth research.<\/jats:p>\n          <jats:p>\n            In this paper, we conduct extensive experiments on two real CXL memory devices based on the 4\n            <jats:sup>th<\/jats:sup>\n            -generation Intel\u00ae Xeon\u00ae Scalable Processor with CXL 1.0 support. Specifically, we run various microbenchmarks not only to evaluate the performance characteristics of CXL memory devices, but also to measure the performance impact of different memory allocation methods. We observe significant performance disparities and allocation inefficiencies, motivating us to innovate the hash design in the CXL-based disaggregated memory system. Lastly, we propose CHash, a highly efficient hashing scheme that adopts a DRAM-CXL memory hybrid storage mechanism. CHash maintains components across different media by carefully designing the hash structure to fully exploit the features of CXL memory devices. Furthermore, CHash implements several acceleration techniques to speed up the key-value (KV) record searches. Some optimizations, including stage buckets, two-level filtering, hashing multiplexing and so on, are also further adopted to improve the overall performance. Extensive experimental results validate the efficiency of CHash in different CXL memory devices, demonstrating that it achieves a 2.2\u00d7 to 9.4\u00d7 speedup for insertions, and a 1.2\u00d7 to 4.5\u00d7 speedup for lookups, all the while maintaining a high load factor (~90%), compared to state-of-the-art hashing schemes.\n          <\/jats:p>","DOI":"10.1145\/3711698","type":"journal-article","created":{"date-parts":[[2025,3,10]],"date-time":"2025-03-10T16:05:24Z","timestamp":1741622724000},"page":"1-22","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["CHash: A High Cost-Performance Hash Design for CXL-based Disaggregated Memory System"],"prefix":"10.1145","volume":"9","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-2333-2123","authenticated-orcid":false,"given":"Mengting","family":"Lu","sequence":"first","affiliation":[{"name":"Alibaba Cloud Computing, Hangzhou, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0001-8416-2124","authenticated-orcid":false,"given":"Gaocong","family":"Liu","sequence":"additional","affiliation":[{"name":"Alibaba Cloud Computing, Hangzhou, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5206-5311","authenticated-orcid":false,"given":"Kun","family":"Wang","sequence":"additional","affiliation":[{"name":"Alibaba Cloud Computing, Hangzhou, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0008-1119-3422","authenticated-orcid":false,"given":"Feng","family":"Zhu","sequence":"additional","affiliation":[{"name":"Alibaba Cloud Computing, Hangzhou, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7215-7619","authenticated-orcid":false,"given":"Shu","family":"Li","sequence":"additional","affiliation":[{"name":"Alibaba Cloud Computing, Hangzhou, China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2025,3,10]]},"reference":[{"key":"e_1_2_1_1_1","volume-title":"accessed","author":"AMD.","year":"2024","unstructured":"AMD. accessed in 2024. 4th Gen AMD EPYC#8482; Processor Architecture. https:\/\/www.amd.com\/en\/campaigns\/epyc-9004-architecture"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/2254756.2254766"},{"key":"e_1_2_1_3_1","volume-title":"accessed","author":"Axboe Jens","year":"2024","unstructured":"Jens Axboe. accessed in 2024. Flexible I\/O tester. https:\/\/github.com\/axboe\/fio"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2023.3241586"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/3183713.3196898"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/1807128.1807152"},{"key":"e_1_2_1_7_1","unstructured":"Intel Corporation. 2017. Intel Optane DC Persistent Memory Products. https:\/\/www.intel.com\/content\/www\/us\/en\/products\/details\/memory-storage\/optane-dc-persistent-memory.html"},{"key":"e_1_2_1_8_1","volume-title":"accessed","author":"Intel Corporation","year":"2024","unstructured":"Intel Corporation. accessed in 2024. 4th Generation Intel\u00ae Xeon\u00ae Scalable Processors. https:\/\/ark.intel.com\/content\/www\/us\/en\/ark\/products\/series\/228622\/4th-generation-intel-xeon-scalable-processors.html"},{"key":"e_1_2_1_9_1","volume-title":"accessed","author":"Intel Corporation","year":"2024","unstructured":"Intel Corporation. accessed in 2024. Intel\u00ae Memory Latency Checker v3.11. https:\/\/www.intel.com\/content\/www\/us\/en\/developer\/articles\/tool\/intelr-memory-latency-checker.html"},{"key":"e_1_2_1_10_1","volume-title":"accessed","author":"Intel Corporation","year":"2024","unstructured":"Intel Corporation. accessed in 2024. New 5th Gen Intel Xeon Processors are Built with AI Acceleration in Every Core. https:\/\/www.intel.com\/content\/www\/us\/en\/newsroom\/news\/5th-gen-xeon-data-center-news.html"},{"volume-title":"accessed","year":"2024","key":"e_1_2_1_11_1","unstructured":"Dormando. accessed in 2024. memcached. https:\/\/memcached.org\/"},{"key":"e_1_2_1_12_1","volume-title":"accessed","author":"Eletronics Samsung","year":"2024","unstructured":"Samsung Eletronics. accessed in 2024. Scalable Memory Development Kit (SMDK) v1.5. https:\/\/github.com\/OpenMPDK\/SMD"},{"key":"e_1_2_1_13_1","volume-title":"accessed","author":"Eletronics Samsung","year":"2024","unstructured":"Samsung Eletronics. accessed in 2024. Sumsung First-512GB CXL Memory Module. https:\/\/news.samsung.com\/global\/samsung-electronics-introduces-industrys-first-512gb-cxl-memory-module"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/588058.588072"},{"key":"e_1_2_1_15_1","volume-title":"accessed","author":"PostgreSQL Global Development Group","year":"2024","unstructured":"PostgreSQL Global Development Group. accessed in 2024. PostgreSQL: The World's Most Advanced Open Source Relational Database. https:\/\/www.postgresql.org\/\/"},{"key":"e_1_2_1_16_1","volume-title":"Halo: A Hybrid PMem-DRAM Persistent Hash Index with Fast Recovery. In SIGMOD '22: International Conference on Management of Data","author":"Hu Daokun","year":"2022","unstructured":"Daokun Hu, Zhiwen Chen, Wenkui Che, Jianhua Sun, and Hao Chen. 2022. Halo: A Hybrid PMem-DRAM Persistent Hash Index with Fast Recovery. In SIGMOD '22: International Conference on Management of Data, Philadelphia, PA, USA, June 12--17, 2022. ACM, 1049--1063."},{"key":"e_1_2_1_17_1","volume-title":"Proceedings of the Neural Information Processing Systems Track on Datasets and Benchmarks 1, NeurIPS Datasets and Benchmarks 2021","author":"Hu Weihua","year":"2021","unstructured":"Weihua Hu, Matthias Fey, Hongyu Ren, Maho Nakata, Yuxiao Dong, and Jure Leskovec. 2021. OGB-LSC: A Large-Scale Challenge for Machine Learning on Graphs. In Proceedings of the Neural Information Processing Systems Track on Datasets and Benchmarks 1, NeurIPS Datasets and Benchmarks 2021, December 2021, virtual,, Joaquin Vanschoren and Sai-Kit Yeung (Eds.)."},{"key":"e_1_2_1_18_1","volume-title":"accessed","author":"SK hynix Inc.","year":"2024","unstructured":"SK hynix Inc. accessed in 2024. SK hynix Introduces Industry's First CXL-based Computational Memory Solution (CMS) at the OCP Global Summit. https:\/\/news.skhynix.com\/sk-hynix-introduces-industrys-first-cxl-based-cms-at-the-ocp-global-summit\/"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540748"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2018.00014"},{"key":"e_1_2_1_21_1","volume-title":"Improving key-value cache performance with heterogeneous memory tiering: A case study of CXL-based memory expansion","author":"Lee KyungSoo","year":"2024","unstructured":"KyungSoo Lee, Sohyun Kim, Joohee Lee, Donguk Moon, Rakie Kim, Honggyu Kim, Hyeongtak Ji, Yunjeong Mun, and Youngpyo Joo. 2024. Improving key-value cache performance with heterogeneous memory tiering: A case study of CXL-based memory expansion. IEEE Micro (2024), 1--11."},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.14778\/3372716.3372728"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/3035918.3064015"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.14778\/3384345.3384355"},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.14778\/3389133.3389134"},{"volume-title":"accessed","year":"2024","key":"e_1_2_1_26_1","unstructured":"Memkind. accessed in 2024. memkind github. https:\/\/github.com\/memkind\/memkind"},{"volume-title":"accessed","year":"2024","key":"e_1_2_1_27_1","unstructured":"Micron. accessed in 2024. CZ120 Memory Expansion Module. https:\/\/www.micron.com\/solutions\/server\/cxl"},{"key":"e_1_2_1_28_1","volume-title":"Write-Optimized Dynamic Hashing for Persistent Memory. In 17th USENIX Conference on File and Storage Technologies, FAST 2019","author":"Nam Moohyeon","year":"2019","unstructured":"Moohyeon Nam, Hokeun Cha, Young-ri Choi, Sam H. Noh, and Beomseok Nam. 2019. Write-Optimized Dynamic Hashing for Persistent Memory. In 17th USENIX Conference on File and Storage Technologies, FAST 2019, Boston, MA, February 25--28, 2019. USENIX Association, 31--44."},{"volume-title":"accessed","year":"2024","key":"e_1_2_1_29_1","unstructured":"Redis. accessed in 2024. Redis. https:\/\/redis.io\/"},{"key":"e_1_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.14778\/3476249.3476286"},{"key":"e_1_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/3613424.3614256"},{"key":"e_1_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/3627703.3650061"},{"key":"e_1_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/3627703.3650061"},{"key":"e_1_2_1_34_1","volume-title":"accessed","author":"Technology Montage","year":"2024","unstructured":"Montage Technology. accessed in 2024. CXL Memory eXpander Controller (MXC). https:\/\/www.montage-tech.com\/MXC"},{"key":"e_1_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.14778\/3025111.3025113"},{"key":"e_1_2_1_36_1","volume-title":"Write-Optimized and High-Performance Hashing Index Scheme for Persistent Memory. In 13th USENIX Symposium on Operating Systems Design and Implementation, OSDI 2018","author":"Zuo Pengfei","year":"2018","unstructured":"Pengfei Zuo, Yu Hua, and Jie Wu. 2018. Write-Optimized and High-Performance Hashing Index Scheme for Persistent Memory. In 13th USENIX Symposium on Operating Systems Design and Implementation, OSDI 2018, Carlsbad, CA, USA, October 8--10, 2018,, Andrea C. Arpaci-Dusseau and Geoff Voelker (Eds.). USENIX Association, 461--476."}],"container-title":["Proceedings of the ACM on Measurement and Analysis of Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3711698","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3711698","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,23]],"date-time":"2025-08-23T02:19:27Z","timestamp":1755915567000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3711698"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,3,6]]},"references-count":36,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2025,3,6]]}},"alternative-id":["10.1145\/3711698"],"URL":"https:\/\/doi.org\/10.1145\/3711698","relation":{},"ISSN":["2476-1249"],"issn-type":[{"type":"electronic","value":"2476-1249"}],"subject":[],"published":{"date-parts":[[2025,3,6]]},"assertion":[{"value":"2025-03-10","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}