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Syst."],"published-print":{"date-parts":[[2025,4,30]]},"abstract":"<jats:p>In recent years, Computing In-Memory (CIM) technology has been proposed to solve the bottleneck of data movement in AI edge designs. In-RRAM Computing (IRC) is a popular architecture due to its low leakage current and high density. However, to integrate some simple computation in memory, the IRC designs often adopt analog operations, which bring new issues to the computation accuracy. In order to speed up the verification of computation results, an accurate behavioral model for the RRAM crossbar array and the peripheral circuits with non-ideal effects is proposed. By using the proposed behavioral model, we build a hierarchical simulation framework for the IRC system to provide runtime errors for circuit design optimization and CNN training. As shown in the experimental results, the simulation accuracy of the IRC system is greatly improved by considering the contribution from peripheral circuits, but the simulation time can be reduced from several hours to 1 minute. The error-aware CNN training with the proposed models efficiently improves the CNN inference accuracy in real applications, which solves the accuracy and efficiency issues in traditional approaches.<\/jats:p>","DOI":"10.1145\/3711830","type":"journal-article","created":{"date-parts":[[2025,1,28]],"date-time":"2025-01-28T16:13:28Z","timestamp":1738080808000},"page":"1-22","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["Error-Aware Training for In-RRAM Computing Design Considering Non-Ideal Effects in RRAM Crossbar Array and Peripheral Circuits"],"prefix":"10.1145","volume":"21","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-0730-1167","authenticated-orcid":false,"given":"Shih-Han","family":"Chang","sequence":"first","affiliation":[{"name":"Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0005-5026-368X","authenticated-orcid":false,"given":"Ray-Hong","family":"Yen","sequence":"additional","affiliation":[{"name":"Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4907-898X","authenticated-orcid":false,"given":"Chien-Nan","family":"Liu","sequence":"additional","affiliation":[{"name":"Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2025,3,15]]},"reference":[{"key":"e_1_3_1_2_2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2880918"},{"key":"e_1_3_1_3_2","first-page":"27","volume-title":"ACM\/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA)","author":"Chi Ping","year":"2016","unstructured":"Ping Chi, Shuangchen Li, Cong Xu, Tao Zhang, Jishen Zhao, Yongpan Liu, Yu Wang, and Yuan Xie. 2016. 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