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Archit. Code Optim."],"published-print":{"date-parts":[[2025,3,31]]},"abstract":"<jats:p>\n            Low-diameter network topologies require non-minimal routing, such as Valiant routing, to avoid network congestion under challenging traffic patterns like the so-called adversarial. However, this mechanism tends to increase the average path length, base latency, and network load. The use of shorter non-minimal paths has the potential to enhance performance, but it may also introduce congestion depending on the traffic patterns. This article introduces\n            <jats:italic>LIA<\/jats:italic>\n            (Latency-Improved Adaptive), a routing mechanism for Dragonfly networks which dynamically exploits minimal and non-minimal paths.\n            <jats:italic>LIA<\/jats:italic>\n            harnesses the traffic counters already present in contemporary switches to determine when it is safe to shorten non-minimal paths and to adjust routing decisions based on their information about the network conditions. Evaluations reveal that\n            <jats:italic>LIA<\/jats:italic>\n            achieves nearly optimal latency, outperforming state-of-the-art adaptive routing mechanisms by reducing latency by up to 30% while maintaining stable throughput and fairness.\n          <\/jats:p>","DOI":"10.1145\/3711914","type":"journal-article","created":{"date-parts":[[2025,1,13]],"date-time":"2025-01-13T11:34:46Z","timestamp":1736768086000},"page":"1-26","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["LIA: Latency-Improved Adaptive routing for Dragonfly networks"],"prefix":"10.1145","volume":"22","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-6611-7015","authenticated-orcid":false,"given":"Mariano","family":"Benito","sequence":"first","affiliation":[{"name":"Computer Sciences, Barcelona Supercomputing Center, Barcelona, Spain and Computer Engineering and Electronics Department, Universidad de Cantabria, Santander, Spain"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5133-1358","authenticated-orcid":false,"given":"Enrique","family":"Vallejo","sequence":"additional","affiliation":[{"name":"Computer Engineering and Electronics Department, Universidad de Cantabria, Santander, Spain"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9591-7078","authenticated-orcid":false,"given":"Ram\u00f3n","family":"Beivide","sequence":"additional","affiliation":[{"name":"Computer Engineering and Electronics Department, Universidad de Cantabria, Santander, Spain"}]}],"member":"320","published-online":{"date-parts":[[2025,3,21]]},"reference":[{"volume-title":"About Aries Hardware Counters","year":"2018","key":"e_1_3_3_2_2","unstructured":"2018. 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