{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,24]],"date-time":"2026-02-24T18:30:05Z","timestamp":1771957805049,"version":"3.50.1"},"reference-count":36,"publisher":"Association for Computing Machinery (ACM)","issue":"1","license":[{"start":{"date-parts":[[2025,3,21]],"date-time":"2025-03-21T00:00:00Z","timestamp":1742515200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"Fonds de recherche du Qu\u00e9bec\u2013Nature et technologies (FRQNT) Doctoral Research Scholarship Program, the Natural Sciences and Engineering Research Council of Canada (NSERC) Discovery","award":["RGPIN-2020-05889"],"award-info":[{"award-number":["RGPIN-2020-05889"]}]},{"name":"Canada CIFAR AI Chairs Program"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Archit. Code Optim."],"published-print":{"date-parts":[[2025,3,31]]},"abstract":"<jats:p>While traditional High-Level Synthesis (HLS) converts \u201chigh-level\u201d C-like programs into hardware automatically, producing high-performance designs still requires hardware expertise. Optimizations such as data partitioning can have a large impact on performance since they directly affect data reuse patterns and the ability to reuse hardware. However, optimizing partitioning is a difficult process since minor changes in the parameter choices can lead to totally unpredictable performance.<\/jats:p>\n          <jats:p>Functional array-based languages have been proposed instead of C-based approaches, as they offer stronger performance guarantees. This article proposes to follow a similar approach and exposes a divide-and-conquer primitive at the algorithmic level to let users partition any arbitrary computation. The compiler is then free to explore different partition shapes to maximize both data and hardware reuse automatically. The main challenge remains that the impact of partitioning is only known much later in the compilation flow. This is due to the hard-to-predict effects of the many optimizations applied during compilation.<\/jats:p>\n          <jats:p>To solve this problem, the partitioning is expressed using a set of symbolic tunable parameters, introduced early in the compilation pipeline. A symbolic performance model is then used in the last compilation stage to predict performance based on the possible values of the tunable parameters. Using this approach, a design space exploration is conducted on an Intel Arria 10 Field Programmable Gate Arrays (FPGAs), and competitive performance is achieved on the classical VGG and TinyYolo neural networks.<\/jats:p>","DOI":"10.1145\/3711926","type":"journal-article","created":{"date-parts":[[2025,1,16]],"date-time":"2025-01-16T11:04:43Z","timestamp":1737025483000},"page":"1-26","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["Maximizing Data and Hardware Reuse for HLS with Early-Stage Symbolic Partitioning"],"prefix":"10.1145","volume":"22","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-1629-8617","authenticated-orcid":false,"given":"Tzung-Han","family":"Juang","sequence":"first","affiliation":[{"name":"Electrical and Computer Engineering, McGill University, Montreal, Canada"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4811-2469","authenticated-orcid":false,"given":"Christophe","family":"Dubach","sequence":"additional","affiliation":[{"name":"McGill University, Montreal, Canada and Mila - Quebec Artificial Intelligence Institute, Montreal, Canada"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2025,3,21]]},"reference":[{"key":"e_1_3_1_2_2","volume-title":"Digital Circuit in C \\(\\lambda\\) aSH: Functional Specifications and Type-Directed Synthesis","author":"Baaij C. P. R.","year":"2015","unstructured":"C. P. R. Baaij. 2015. Digital Circuit in C \\(\\lambda\\) aSH: Functional Specifications and Type-Directed Synthesis. Ph. D. Dissertation. University of Twente, Netherlands."},{"key":"e_1_3_1_3_2","volume-title":"Proceedings of the 2019 IEEE 5th International Conference on Computer and Communications (ICCC \u201919)","author":"Bai Zhihong","year":"2019","unstructured":"Zhihong Bai, Haoxin Fan, Lingzhi Liu, Li Liu, and Dong Wang. 2019. An OpenCL-based FPGA accelerator with the Winograd\u2019s minimal filtering algorithm for convolution neuron networks. In Proceedings of the 2019 IEEE 5th International Conference on Computer and Communications (ICCC \u201919)."},{"key":"e_1_3_1_4_2","volume-title":"Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW \u201918)","author":"Baskin Chaim","year":"2018","unstructured":"Chaim Baskin, Natan Liss, Evgenii Zheltonozhskii, Alex M. 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Retrieved January 19 2025 from https:\/\/www.intel.com\/content\/www\/us\/en\/docs\/programmable\/683846"},{"key":"e_1_3_1_11_2","doi-asserted-by":"publisher","DOI":"10.1145\/3385412.3385983"},{"key":"e_1_3_1_12_2","volume-title":"Proceedings of the Workshop on Open-Source EDA Technology (WOSET \u201921)","author":"Eldridge Schuyler","year":"2021","unstructured":"Schuyler Eldridge, Prithayan Barua, Aliaksei Chapyzhenka, Adam Izraelevitz, Jack Koenig, Chris Lattner, Andrew Lenharth, George Leontiev, Fabian Schuiki, Ram Sunder, et\u00a0al. 2021. MLIR as hardware compiler infrastructure. In Proceedings of the Workshop on Open-Source EDA Technology (WOSET \u201921)."},{"key":"e_1_3_1_13_2","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18074.2021.9586110"},{"key":"e_1_3_1_14_2","doi-asserted-by":"publisher","DOI":"10.1145\/2145694.2145712"},{"key":"e_1_3_1_15_2","article-title":"AutoPhase: Juggling HLS phase orderings in random forests with deep reinforcement learning","author":"Haj-Ali Ameer","year":"2020","unstructured":"Ameer Haj-Ali, Qijing Jenny Huang, John Xiang, William Moses, Krste Asanovic, John Wawrzynek, and Ion Stoica. 2020. AutoPhase: Juggling HLS phase orderings in random forests with deep reinforcement learning. In Proceedings of the 3rd Conference on Machine Learning and Systems (MLSys \u201920).","journal-title":"Proceedings of the 3rd Conference on Machine Learning and Systems (MLSys \u201920)."},{"key":"e_1_3_1_16_2","volume-title":"Proceedings of the 2018 Design, Automation, and Test in Europe Conference and Exhibition (DATE \u201918)","author":"Hsiao Hsuan","year":"2018","unstructured":"Hsuan Hsiao and Jason H. Anderson. 2018. Sensei: An area-reduction advisor for FPGA high-level synthesis. In Proceedings of the 2018 Design, Automation, and Test in Europe Conference and Exhibition (DATE \u201918). IEEE."},{"key":"e_1_3_1_17_2","volume-title":"Proceedings of the 2020 ACM\/IEEE 47th Annual International Symposium on Computer Architecture (ISCA \u201920)","author":"Jo Gangwon","year":"2020","unstructured":"Gangwon Jo, Heehoon Kim, Jeesoo Lee, and Jaejin Lee. 2020. SOFF: An OpenCL high-level synthesis framework for FPGAs. In Proceedings of the 2020 ACM\/IEEE 47th Annual International Symposium on Computer Architecture (ISCA \u201920). IEEE."},{"issue":"5","key":"e_1_3_1_18_2","first-page":"114","article-title":"Let coarse-grained resources be shared: Mapping entire neural networks on FPGAs","volume":"22","author":"Juang Tzung-Han","year":"2023","unstructured":"Tzung-Han Juang, Christof Schlaak, and Christophe Dubach. 2023. Let coarse-grained resources be shared: Mapping entire neural networks on FPGAs. ACM Transactions on Embedded Computing Systems 22, 5s (2023), Article 114, 23 pages.","journal-title":"ACM Transactions on Embedded Computing Systems"},{"key":"e_1_3_1_19_2","doi-asserted-by":"publisher","DOI":"10.1145\/3192366.3192379"},{"key":"e_1_3_1_20_2","doi-asserted-by":"publisher","DOI":"10.1145\/3315454.3329957"},{"key":"e_1_3_1_21_2","doi-asserted-by":"publisher","DOI":"10.1145\/3315454.3329957"},{"key":"e_1_3_1_22_2","doi-asserted-by":"publisher","DOI":"10.1145\/3289602.3293910"},{"key":"e_1_3_1_23_2","volume-title":"Proceedings of the 2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS \u201919)","author":"Lammie Corey","year":"2019","unstructured":"Corey Lammie, Wei Xiang, and Mostafa Rahimi Azghadi. 2019. Accelerating deterministic and stochastic binarized neural networks on FPGAs using OpenCL. In Proceedings of the 2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS \u201919). IEEE."},{"key":"e_1_3_1_24_2","unstructured":"Huyuan Li. 2017. Acceleration of deep learning on FPGA. Ph.D. Thesis. University of Windsor Canada."},{"key":"e_1_3_1_25_2","volume-title":"Proceedings of the 39th International Conference on Computer-Aided Design","author":"Minutoli Marco","year":"2020","unstructured":"Marco Minutoli, Vito Giovanni Castellana, Cheng Tan, Joseph Manzano, Vinay Amatya, Antonino Tumeo, David Brooks, and Gu-Yeon Wei. 2020. SODA: A new synthesis infrastructure for agile hardware design of machine learning accelerators. In Proceedings of the 39th International Conference on Computer-Aided Design."},{"key":"e_1_3_1_26_2","doi-asserted-by":"publisher","DOI":"10.1145\/3385412.3385974"},{"issue":"11","key":"e_1_3_1_27_2","article-title":"AnyHLS: High-level synthesis with partial evaluation","volume":"39","author":"\u00d6zkan M. Akif","year":"2020","unstructured":"M. Akif \u00d6zkan, Ars\u00e8ne P\u00e9rard-Gayot, Richard Membarth, Philipp Slusallek, Roland Lei\u00dfa, Sebastian Hack, J\u00fcrgen Teich, and Frank Hannig. 2020. AnyHLS: High-level synthesis with partial evaluation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 39, 11 (2020), 3202\u20133214.","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"e_1_3_1_28_2","volume-title":"Advances in Neural Information Processing Systems 32","author":"Paszke Adam","year":"2019","unstructured":"Adam Paszke, Sam Gross, Francisco Massa, Adam Lerer, James Bradbury, Gregory Chanan, Trevor Killeen, Zeming Lin, Natalia Gimelshein, Luca Antiga, et al.. 2019. PyTorch: An imperative style, high-performance deep learning library. In Advances in Neural Information Processing Systems 32. Curran Associates, 1\u201312."},{"issue":"5","key":"e_1_3_1_29_2","article-title":"COSMOS: Coordination of high-level synthesis and memory optimization for hardware accelerators","volume":"16","author":"Piccolboni Luca","year":"2017","unstructured":"Luca Piccolboni, Paolo Mantovani, Giuseppe Di Guglielmo, and Luca P. Carloni. 2017. COSMOS: Coordination of high-level synthesis and memory optimization for hardware accelerators. ACM Transactions on Embedded Computing Systems (TECS) 16, 5s (2017), Article 150, 22 pages.","journal-title":"ACM Transactions on Embedded Computing Systems (TECS)"},{"issue":"3","key":"e_1_3_1_30_2","article-title":"Programming heterogeneous systems from an image processing DSL","volume":"14","author":"Pu Jing","year":"2017","unstructured":"Jing Pu, Steven Bell, Xuan Yang, Jeff Setter, Stephen Richardson, Jonathan Ragan-Kelley, and Mark Horowitz. 2017. Programming heterogeneous systems from an image processing DSL. ACM Transactions on Architecture and Code Optimization 14, 3 (2017), Article 26, 25 pages.","journal-title":"ACM Transactions on Architecture and Code Optimization"},{"issue":"2","key":"e_1_3_1_31_2","first-page":"16","article-title":"Memory-aware functional IR for higher-level synthesis of accelerators","volume":"19","author":"Schlaak Christof","year":"2022","unstructured":"Christof Schlaak, Tzung-Han Juang, and Christophe Dubach. 2022. Memory-aware functional IR for higher-level synthesis of accelerators. ACM Transactions on Architecture and Code Optimization 19, 2 (2022), Article 16, 26 pages.","journal-title":"ACM Transactions on Architecture and Code Optimization"},{"key":"e_1_3_1_32_2","doi-asserted-by":"publisher","DOI":"10.1145\/3519941.3535069"},{"issue":"4","key":"e_1_3_1_33_2","article-title":"AutoDSE: Enabling software programmers to design efficient FPGA accelerators","volume":"27","author":"Sohrabizadeh Atefeh","year":"2022","unstructured":"Atefeh Sohrabizadeh, Cody Hao Yu, Min Gao, and Jason Cong. 2022. AutoDSE: Enabling software programmers to design efficient FPGA accelerators. ACM Transactions on Design Automation of Electronic Systems 27, 4 (2022), Article 32, 27 pages.","journal-title":"ACM Transactions on Design Automation of Electronic Systems"},{"issue":"2","key":"e_1_3_1_34_2","article-title":"Winols: A large-tiling sparse Winograd CNN accelerator on FPGAs","volume":"21","author":"Xie Kunpeng","year":"2024","unstructured":"Kunpeng Xie, Ye Lu, Xinyu He, Dezhi Yi, Huijuan Dong, and Yao Chen. 2024. Winols: A large-tiling sparse Winograd CNN accelerator on FPGAs. ACM Transactions on Architecture and Code Optimization 21, 2 (2024), Article 31, 24 pages.","journal-title":"ACM Transactions on Architecture and Code Optimization"},{"key":"e_1_3_1_35_2","volume-title":"Proceedings of the 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM \u201919)","author":"Xu Ke","year":"2019","unstructured":"Ke Xu, Xiaoyun Wang, and Dong Wang. 2019. A scalable OpenCL-based FPGA accelerator for YOLOv2. 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Performance modeling and directives optimization for high-level synthesis on FPGA. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 39, 7 (2019), 1428\u20131441.","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"}],"container-title":["ACM Transactions on Architecture and Code Optimization"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3711926","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3711926","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T01:18:10Z","timestamp":1750295890000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3711926"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,3,21]]},"references-count":36,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2025,3,31]]}},"alternative-id":["10.1145\/3711926"],"URL":"https:\/\/doi.org\/10.1145\/3711926","relation":{},"ISSN":["1544-3566","1544-3973"],"issn-type":[{"value":"1544-3566","type":"print"},{"value":"1544-3973","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,3,21]]},"assertion":[{"value":"2024-07-07","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2024-12-25","order":2,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2025-03-21","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}