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Critical real-time systems are traditionally custom-designed, featuring redundancy for guaranteeing fault resilience. The downsides of such custom systems are typically weight, power, energy, space, and cost, compared to\n            <jats:italic>Commercial Off-the-Shelf<\/jats:italic>\n            (COTS) solutions. We explored the use of COTS in critical real-time environments by designing a CPU-FPGA heterogeneous system, which features an ARM CPU, running a modified version of FreeRTOS and an FPGA, on which the fault-detector and the scheduler are synthesized, in a redundant configuration for increasing fault resiliency. Moving the scheduler to the FPGA increases its fault resiliency while removing the periodic scheduler execution overhead from the CPU, making the scheduler overhead negligible and allowing for an elevated time resolution: the tasks can almost completely utilize the CPU time. Similarly, synthesizing the fault detector on the FPGA allows the execution of the fault detection in a fault-tolerant way without wasting CPU time. Transient fault resiliency in application tasks is achieved via fault detection and the subsequent fault recovery via re-execution. The fault detector implemented on FPGA uses a machine learning technique to model the behavior of tasks (offline and possibly online) and analyses it during their execution. Regarding fault recovery, the scheduler on the FPGA features a novel mixed-criticality scheduling algorithm that manages re-executions, ensuring the meeting of tasks\u2019 timing constraints. The fault detection showed noticeable results while providing a lower overhead than general-purpose software techniques for improving fault resiliency. To the best of our knowledge, the integrated CPU-FPGA version of the system, featuring fault-tolerance and real-time scheduling, is a novel contribution that may enable the use of low-cost and fast COTS components in critical real-time environments. The source code for both hardware and software was released as open source.\n          <\/jats:p>\n          <jats:p\/>","DOI":"10.1145\/3712062","type":"journal-article","created":{"date-parts":[[2025,1,17]],"date-time":"2025-01-17T10:18:17Z","timestamp":1737109097000},"page":"1-50","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["HeterogeneousRTOS: A CPU-FPGA Real-Time OS for Fault Tolerance on COTS at Near-Zero Timing Cost"],"prefix":"10.1145","volume":"24","author":[{"ORCID":"https:\/\/orcid.org\/0009-0003-9355-9769","authenticated-orcid":false,"given":"Francesco","family":"Ratti","sequence":"first","affiliation":[{"name":"Dipartimento di Elettronica e Informazione, Politecnico di Milano, Milano, Italy"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7298-8252","authenticated-orcid":false,"given":"Johannes","family":"Kn\u00f6dtel","sequence":"additional","affiliation":[{"name":"Institute of Applied Microelectronics and Computer Engineering, Universit\u00e4t Rostock, Rostock, Germany"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9687-6247","authenticated-orcid":false,"given":"Marc","family":"Reichenbach","sequence":"additional","affiliation":[{"name":"Institute of Applied Microelectronics and Computer Engineering, Universit\u00e4t Rostock, Rostock, Germany"}]}],"member":"320","published-online":{"date-parts":[[2025,2,8]]},"reference":[{"key":"e_1_3_2_2_1","unstructured":"2023. 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