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Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2025,3,31]]},"abstract":"<jats:p>Area and reliability optimization have become the primary constraints in circuits logic synthesis. To address the increasing area and transient fault susceptibility in combinational circuits, we propose a high-dimensional genetic algorithm (HGA). HGA adopts an evolutionary scheme based on ternary tree, and uses adaptive crossover operator and flight operator to jump out of local optimum. Moreover, based on the HGA, we propose an area and reliability optimization method (AROM) for mixed polarity Reed-Muller logic circuits, which searches the best polarity with minimum area and soft error rate. The experimental results confirm that AROM can search for more desirable nondominated solutions in less time compared to existing optimization methods, and can be used as an effective electronic design automation tool for multi-objective optimization.<\/jats:p>","DOI":"10.1145\/3712591","type":"journal-article","created":{"date-parts":[[2025,1,17]],"date-time":"2025-01-17T10:18:32Z","timestamp":1737109112000},"page":"1-22","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["An Efficient Area and Reliability Optimization Method for MPRM Circuits Based on High-dimensional Genetic Algorithm"],"prefix":"10.1145","volume":"30","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-6460-7480","authenticated-orcid":false,"given":"Yuhao","family":"Zhou","sequence":"first","affiliation":[{"name":"Tongji University, Shanghai, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5829-8423","authenticated-orcid":false,"given":"Jianhui","family":"Jiang","sequence":"additional","affiliation":[{"name":"School of software engineering, Tongji University, Shanghai, China and Sanda University, Shanghai, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7041-8582","authenticated-orcid":false,"given":"Zhenxue","family":"He","sequence":"additional","affiliation":[{"name":"Hebei Agricultural University, Baoding, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7887-6510","authenticated-orcid":false,"given":"Ying","family":"Zhang","sequence":"additional","affiliation":[{"name":"Tongji University, Shanghai, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6014-5135","authenticated-orcid":false,"given":"Chengcheng","family":"Chen","sequence":"additional","affiliation":[{"name":"Shanghai Maritime University, Shanghai, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0770-6690","authenticated-orcid":false,"given":"Zhanhui","family":"Shi","sequence":"additional","affiliation":[{"name":"Tongji University, Shanghai, China"}]},{"ORCID":"https:\/\/orcid.org\/0009-0000-2717-5212","authenticated-orcid":false,"given":"Wei","family":"Zhang","sequence":"additional","affiliation":[{"name":"Tongji University, Shanghai, China"}]},{"ORCID":"https:\/\/orcid.org\/0009-0002-5391-3391","authenticated-orcid":false,"given":"Keying","family":"Yang","sequence":"additional","affiliation":[{"name":"Tongji University, Shanghai, China"}]}],"member":"320","published-online":{"date-parts":[[2025,2,6]]},"reference":[{"key":"e_1_3_1_2_2","doi-asserted-by":"publisher","DOI":"10.1109\/TBME.2021.3093542"},{"key":"e_1_3_1_3_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2022.3149720"},{"key":"e_1_3_1_4_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2021.3072772"},{"key":"e_1_3_1_5_2","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2021.3050694"},{"key":"e_1_3_1_6_2","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2011.1"},{"key":"e_1_3_1_7_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2024.3485577"},{"key":"e_1_3_1_8_2","doi-asserted-by":"publisher","DOI":"10.1145\/3587818"},{"key":"e_1_3_1_9_2","doi-asserted-by":"crossref","first-page":"105674","DOI":"10.1016\/j.mejo.2022.105674","article-title":"A 1T2M memristor-based logic circuit and its applications","volume":"132","author":"Su B.","year":"2023","unstructured":"B. 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