{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,27]],"date-time":"2025-06-27T15:10:08Z","timestamp":1751037008513,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":15,"publisher":"ACM","content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2025,6,30]]},"DOI":"10.1145\/3716368.3735174","type":"proceedings-article","created":{"date-parts":[[2025,6,27]],"date-time":"2025-06-27T13:58:23Z","timestamp":1751032703000},"page":"292-297","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["ASF-CRB: an Energy-Efficient Activity-Balanced Charge-Recycling Bus Architecture Based on Alternate Signal Flipping"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-5436-0066","authenticated-orcid":false,"given":"Xiangyu","family":"Ran","sequence":"first","affiliation":[{"name":"Shanghai Jiao Tong University, Shanghai, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9954-9025","authenticated-orcid":false,"given":"Chuxiong","family":"Lin","sequence":"additional","affiliation":[{"name":"Shanghai Jiao Tong University, Shanghai, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9147-3756","authenticated-orcid":false,"given":"Jieyu","family":"Li","sequence":"additional","affiliation":[{"name":"Shanghai Jiao Tong University, Shanghai, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7753-644X","authenticated-orcid":false,"given":"Weifeng","family":"He","sequence":"additional","affiliation":[{"name":"Shanghai Jiao Tong University, Shanghai, China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2025,6,29]]},"reference":[{"key":"e_1_3_3_1_1_2","doi-asserted-by":"publisher","DOI":"10.1109\/5.920580"},{"key":"e_1_3_3_1_2_2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2036761"},{"key":"e_1_3_3_1_3_2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2021.3095343"},{"key":"e_1_3_3_1_4_2","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2018.8357077"},{"key":"e_1_3_3_1_5_2","doi-asserted-by":"crossref","first-page":"311","DOI":"10.1109\/TVLSI.2008.2004549","article-title":"CMOS Driver-Receiver Pair for Low-Swing Signaling for Low Energy On-Chip Interconnects","volume":"17","author":"Garc\u00cda Montesdeoca J. C.","year":"2009","unstructured":"J. C. Garc\u00cda Montesdeoca, et al. 2009. CMOS Driver-Receiver Pair for Low-Swing Signaling for Low Energy On-Chip Interconnects. In\u00a0IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17, 2 (2009), 311-316.","journal-title":"In\u00a0IEEE Transactions on Very Large Scale Integration (VLSI) Systems"},{"key":"e_1_3_3_1_6_2","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2003.1221224"},{"key":"e_1_3_3_1_7_2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.910807"},{"key":"e_1_3_3_1_8_2","volume-title":"Voltage-Stacked GPUs: A Control Theory Driven Cross-Layer Solution for Practical Voltage Stacking in GPUs. 51st Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO). 390-402","author":"A.","year":"2018","unstructured":"A. Zou\u00a0et al. 2018. Voltage-Stacked GPUs: A Control Theory Driven Cross-Layer Solution for Practical Voltage Stacking in GPUs. 51st Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO). 390-402."},{"key":"e_1_3_3_1_9_2","first-page":"262","article-title":"A 95fJ\/b current-mode transceiver for 10mm on-chip interconnect.\u00a02013 IEEE International Solid-State Circuits Conference (ISSCC)","author":"Lee S. -K.","year":"2013","unstructured":"S. -K. Lee et al. 2013. A 95fJ\/b current-mode transceiver for 10mm on-chip interconnect.\u00a02013 IEEE International Solid-State Circuits Conference (ISSCC). IEEE, 262-263.","journal-title":"IEEE"},{"key":"e_1_3_3_1_10_2","doi-asserted-by":"crossref","unstructured":"M. A. Anders\u00a0et al. 2020. Reconfigurable Transient Current-Mode Global Interconnect Circuits in 10nm CMOS for High-Performance Processors with Wide Voltage-Frequency Operating Range.\u00a02020 IEEE International Solid-State Circuits Conference (ISSCC). IEEE 396-398","DOI":"10.1109\/ISSCC19947.2020.9063158"},{"key":"e_1_3_3_1_11_2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2381637"},{"key":"e_1_3_3_1_12_2","first-page":"454","article-title":"A 78.8fJ\/b\/mm 12.0Gb\/s\/Wire Capacitively Driven On-Chip Link Over 5.6mm with an FFE-Combined Ground-Forcing Biasing Technique for DRAM Global Bus Line in 65nm CMOS.\u00a02022 IEEE International Solid-State Circuits Conference (ISSCC)","author":"Lee S.","year":"2022","unstructured":"S. Lee et al. 2022. A 78.8fJ\/b\/mm 12.0Gb\/s\/Wire Capacitively Driven On-Chip Link Over 5.6mm with an FFE-Combined Ground-Forcing Biasing Technique for DRAM Global Bus Line in 65nm CMOS.\u00a02022 IEEE International Solid-State Circuits Conference (ISSCC). IEEE, 454-456.","journal-title":"IEEE"},{"key":"e_1_3_3_1_13_2","doi-asserted-by":"publisher","DOI":"10.1109\/4.375962"},{"key":"e_1_3_3_1_14_2","first-page":"400","article-title":"A 0.1pJ\/b 5-to-10Gb\/s charge-recycling stacked low-power I\/O for on-chip signaling in 45nm CMOS SOI.\u00a02013 IEEE International Solid-State Circuits Conference (ISSCC)","author":"Y.","year":"2013","unstructured":"Y. Liu\u00a0et al. 2013. A 0.1pJ\/b 5-to-10Gb\/s charge-recycling stacked low-power I\/O for on-chip signaling in 45nm CMOS SOI.\u00a02013 IEEE International Solid-State Circuits Conference (ISSCC). IEEE, 400-401.","journal-title":"IEEE"},{"key":"e_1_3_3_1_15_2","first-page":"156","article-title":"A 6.5-to-23.3fJ\/b\/mm balanced charge-recycling bus in 16nm FinFET CMOS at 1.7-to-2.6Gb\/s\/wire with clock forwarding and low-crosstalk contraflow wiring.\u00a02016 IEEE International Solid-State Circuits Conference (ISSCC)","author":"J. M.","year":"2016","unstructured":"J. M. Wilson\u00a0et al. 2016. A 6.5-to-23.3fJ\/b\/mm balanced charge-recycling bus in 16nm FinFET CMOS at 1.7-to-2.6Gb\/s\/wire with clock forwarding and low-crosstalk contraflow wiring.\u00a02016 IEEE International Solid-State Circuits Conference (ISSCC). IEEE, 156-157.","journal-title":"IEEE"}],"event":{"name":"GLSVLSI '25: Great Lakes Symposium on VLSI 2025","sponsor":["SIGDA ACM Special Interest Group on Design Automation"],"location":"New Orleans LA USA","acronym":"GLSVLSI '25"},"container-title":["Proceedings of the Great Lakes Symposium on VLSI 2025"],"original-title":[],"deposited":{"date-parts":[[2025,6,27]],"date-time":"2025-06-27T14:38:08Z","timestamp":1751035088000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3716368.3735174"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,6,29]]},"references-count":15,"alternative-id":["10.1145\/3716368.3735174","10.1145\/3716368"],"URL":"https:\/\/doi.org\/10.1145\/3716368.3735174","relation":{},"subject":[],"published":{"date-parts":[[2025,6,29]]},"assertion":[{"value":"2025-06-29","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}