{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,27]],"date-time":"2025-06-27T15:10:07Z","timestamp":1751037007610,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":22,"publisher":"ACM","content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2025,6,30]]},"DOI":"10.1145\/3716368.3735192","type":"proceedings-article","created":{"date-parts":[[2025,6,27]],"date-time":"2025-06-27T14:00:26Z","timestamp":1751032826000},"page":"215-220","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Alchemy : A Methodology for Scalable RTL Design Space Exploration"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0009-0002-8931-055X","authenticated-orcid":false,"given":"Ryan","family":"Swann","sequence":"first","affiliation":[{"name":"Electrical and Computer Engineering, Oklahoma State University, Stillwater, Oklahoma, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8767-390X","authenticated-orcid":false,"given":"James","family":"Stine","sequence":"additional","affiliation":[{"name":"Electrical and Computer Engineering, Oklahoma State University, Stillwater, Oklahoma, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2025,6,29]]},"reference":[{"key":"e_1_3_3_1_2_2","doi-asserted-by":"publisher","unstructured":"2013. IEEE Standard for SystemVerilog\u2013Unified Hardware Design Specification and Verification Language. IEEE Std 1800-2012 (Revision of IEEE Std 1800-2009) (2013) 1\u20131315. 10.1109\/IEEESTD.2013.6469140","DOI":"10.1109\/IEEESTD.2013.6469140"},{"key":"e_1_3_3_1_3_2","doi-asserted-by":"publisher","DOI":"10.5555\/6448"},{"key":"e_1_3_3_1_4_2","doi-asserted-by":"publisher","DOI":"10.1145\/3519939.3523436"},{"key":"e_1_3_3_1_5_2","doi-asserted-by":"publisher","DOI":"10.1145\/3289602.3293991"},{"key":"e_1_3_3_1_6_2","doi-asserted-by":"publisher","DOI":"10.1109\/ARITH.2001.930101"},{"key":"e_1_3_3_1_7_2","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-30436-1_24"},{"key":"e_1_3_3_1_8_2","doi-asserted-by":"publisher","unstructured":"Samuel Coward Theo Drane and George\u00a0A. Constantinides. 2024. ROVER: RTL Optimization via Verified E-Graph Rewriting. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 43 12 (2024) 4687\u20134700. 10.1109\/TCAD.2024.3410154","DOI":"10.1109\/TCAD.2024.3410154"},{"key":"e_1_3_3_1_9_2","doi-asserted-by":"publisher","unstructured":"Kalyanmoy Deb Amrit Pratap Sameer Agarwal and Thirunavukarasu Meyarivan. 2002. A fast and elitist multiobjective genetic algorithm: NSGA-II. IEEE Transactions on Evolutionary Computation 6 2 (2002) 182\u2013197. 10.1109\/4235.996017","DOI":"10.1109\/4235.996017"},{"key":"e_1_3_3_1_10_2","volume-title":"tdene\/synth_opt_adders","author":"Ene Teodor-Dumitru","year":"2023","unstructured":"Teodor-Dumitru Ene, Unai Martinez-Corral, Joaquin Raha, Matres, James\u00a0E. Stine, and Hakan \u00c7elik. 2023. tdene\/synth_opt_adders. https:\/\/github.com\/tdene\/synth_opt_adders"},{"key":"e_1_3_3_1_11_2","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD53106.2021.00030"},{"key":"e_1_3_3_1_12_2","volume-title":"Design patterns: elements of reusable object-oriented software","author":"Gamma Erich","year":"1995","unstructured":"Erich Gamma, Richard Helm, Ralph Johnson, and John Vlissides. 1995. Design patterns: elements of reusable object-oriented software. Addison-Wesley Longman Publishing Co., Inc., USA."},{"key":"e_1_3_3_1_13_2","unstructured":"Joel Jones. 2003. Abstract Syntax Tree Implementation Idioms. Pattern Languages of Program Design (2003). http:\/\/hillside.net\/plop\/plop2003\/Papers\/Jones-ImplementingASTs.pdf Proceedings of the 10th Conference on Pattern Languages of Programs (PLoP2003) http:\/\/hillside.net\/plop\/plop2003\/papers.html."},{"key":"e_1_3_3_1_14_2","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2001.913298"},{"key":"e_1_3_3_1_15_2","doi-asserted-by":"publisher","DOI":"10.1145\/2435264.2435287"},{"key":"e_1_3_3_1_16_2","doi-asserted-by":"publisher","DOI":"10.5555\/97670"},{"key":"e_1_3_3_1_17_2","doi-asserted-by":"publisher","unstructured":"Anushree Mahapatra and Benjamin\u00a0Carrion Schafer. 2019. VeriIntel2C: Abstracting RTL to C to maximize High-Level Synthesis Design Space Exploration. Integration 64 (2019) 1\u201312. 10.1016\/j.vlsi.2018.03.011","DOI":"10.1016\/j.vlsi.2018.03.011"},{"key":"e_1_3_3_1_18_2","doi-asserted-by":"crossref","DOI":"10.6028\/NIST.FIPS.197","volume-title":"Advanced Encryption Standard (AES)","author":"Standards National\u00a0Institute of","year":"2001","unstructured":"National\u00a0Institute of Standards and Technology (NIST). 2001. Advanced Encryption Standard (AES). FIPS Publication 197. National Institute of Standards and Technology. https:\/\/nvlpubs.nist.gov\/nistpubs\/FIPS\/NIST.FIPS.197.pdf Available online: https:\/\/nvlpubs.nist.gov\/nistpubs\/FIPS\/NIST.FIPS.197.pdf."},{"key":"e_1_3_3_1_19_2","doi-asserted-by":"publisher","unstructured":"Jack Sklansky. 1960. Conditional-Sum Addition Logic. IRE Transactions on Electronic Computers EC-9 2 (1960) 226\u2013231. 10.1109\/TEC.1960.5219822","DOI":"10.1109\/TEC.1960.5219822"},{"key":"e_1_3_3_1_20_2","doi-asserted-by":"publisher","unstructured":"Ryan Swann and James Stine. 2023. Evaluation of a Modular Approach to AES Hardware Architecture and Optimization. Journal of Signal Processing Systems 95 7 (01 Jul 2023) 797\u2013813. 10.1007\/s11265-022-01832-w","DOI":"10.1007\/s11265-022-01832-w"},{"key":"e_1_3_3_1_21_2","doi-asserted-by":"publisher","DOI":"10.1109\/IEEECONF53345.2021.9723104"},{"key":"e_1_3_3_1_22_2","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2010.75"},{"key":"e_1_3_3_1_23_2","doi-asserted-by":"publisher","unstructured":"Max Willsey Chandrakana Nandi Yisu\u00a0Remy Wang Oliver Flatt Zachary Tatlock and Pavel Panchekha. 2021. egg: Fast and extensible equality saturation. Proc. ACM Program. Lang. 5 POPL Article 23 (Jan. 2021) 29\u00a0pages. 10.1145\/3434304","DOI":"10.1145\/3434304"}],"event":{"name":"GLSVLSI '25: Great Lakes Symposium on VLSI 2025","sponsor":["SIGDA ACM Special Interest Group on Design Automation"],"location":"New Orleans LA USA","acronym":"GLSVLSI '25"},"container-title":["Proceedings of the Great Lakes Symposium on VLSI 2025"],"original-title":[],"deposited":{"date-parts":[[2025,6,27]],"date-time":"2025-06-27T14:37:05Z","timestamp":1751035025000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3716368.3735192"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,6,29]]},"references-count":22,"alternative-id":["10.1145\/3716368.3735192","10.1145\/3716368"],"URL":"https:\/\/doi.org\/10.1145\/3716368.3735192","relation":{},"subject":[],"published":{"date-parts":[[2025,6,29]]},"assertion":[{"value":"2025-06-29","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}