{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,19]],"date-time":"2026-06-19T02:43:19Z","timestamp":1781836999232,"version":"3.54.5"},"publisher-location":"New York, NY, USA","reference-count":9,"publisher":"ACM","content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2025,6,30]]},"DOI":"10.1145\/3716368.3735221","type":"proceedings-article","created":{"date-parts":[[2025,6,27]],"date-time":"2025-06-27T14:00:26Z","timestamp":1751032826000},"page":"221-226","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["A Machine Learning-Assisted Placement Flow with Pin Accessibility Awareness"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0009-0001-4766-4758","authenticated-orcid":false,"given":"Min-Feng","family":"Hsieh","sequence":"first","affiliation":[{"name":"National Tsing Hua University, Hsinchu, Taiwan"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3435-0418","authenticated-orcid":false,"given":"Ting-Chi","family":"Wang","sequence":"additional","affiliation":[{"name":"National Tsing Hua University, Hsinchu, Taiwan"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2025,6,29]]},"reference":[{"key":"e_1_3_3_1_2_2","doi-asserted-by":"publisher","DOI":"10.1145\/3036669.3036679"},{"key":"e_1_3_3_1_3_2","doi-asserted-by":"crossref","unstructured":"Andrew\u00a0B Kahng Jian Kuang Wen-Hao Liu and Bangqi Xu. 2021. In-route pin access-driven placement refinement for improved detailed routing convergence. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 41 3 (2021) 784\u2013788.","DOI":"10.1109\/TCAD.2021.3066528"},{"key":"e_1_3_3_1_4_2","doi-asserted-by":"publisher","DOI":"10.1109\/NEWCAS57931.2023.10198031"},{"key":"e_1_3_3_1_5_2","doi-asserted-by":"publisher","DOI":"10.1145\/2717764.2723572"},{"key":"e_1_3_3_1_6_2","unstructured":"FreeCores. 2009. AVS AES. https:\/\/github.com\/freecores\/avs_aes."},{"key":"e_1_3_3_1_7_2","doi-asserted-by":"crossref","unstructured":"Fulvio Corno Matteo\u00a0Sonza Reorda and Giovanni Squillero. 2000. RT-level ITC\u201999 benchmarks and first ATPG results. IEEE Design & Test 17 3 (2000) 44\u201353.","DOI":"10.1109\/54.867894"},{"key":"e_1_3_3_1_8_2","unstructured":"UltraEmbedded. 2014. RISC-V CPU Core (RV32IM). https:\/\/github.com\/ultraembedded\/riscv."},{"key":"e_1_3_3_1_9_2","doi-asserted-by":"crossref","unstructured":"Amir Yazdanbakhsh Divya Mahajan Hadi Esmaeilzadeh and Pejman Lotfi-Kamran. 2016. AxBench: A multiplatform benchmark suite for approximate computing. IEEE Design & Test 34 2 (2016) 60\u201368.","DOI":"10.1109\/MDAT.2016.2630270"},{"key":"e_1_3_3_1_10_2","unstructured":"Si2. 2008. NanGate 45nm Open Cell Library. https:\/\/si2.org\/open-cell-library\/."}],"event":{"name":"GLSVLSI '25: Great Lakes Symposium on VLSI 2025","location":"New Orleans LA USA","acronym":"GLSVLSI '25","sponsor":["SIGDA ACM Special Interest Group on Design Automation"]},"container-title":["Proceedings of the Great Lakes Symposium on VLSI 2025"],"original-title":[],"deposited":{"date-parts":[[2025,6,27]],"date-time":"2025-06-27T14:37:31Z","timestamp":1751035051000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3716368.3735221"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,6,29]]},"references-count":9,"alternative-id":["10.1145\/3716368.3735221","10.1145\/3716368"],"URL":"https:\/\/doi.org\/10.1145\/3716368.3735221","relation":{},"subject":[],"published":{"date-parts":[[2025,6,29]]},"assertion":[{"value":"2025-06-29","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}