{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,27]],"date-time":"2025-06-27T15:10:06Z","timestamp":1751037006344,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":24,"publisher":"ACM","funder":[{"name":"NSF","award":["2228028"],"award-info":[{"award-number":["2228028"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2025,6,30]]},"DOI":"10.1145\/3716368.3735277","type":"proceedings-article","created":{"date-parts":[[2025,6,27]],"date-time":"2025-06-27T13:58:23Z","timestamp":1751032703000},"page":"817-822","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Maximizing Sub-Array Resource Utilization in Digital Processing-in-Memory: A Versatile Hardware-Aware Approach"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0009-0006-0295-3165","authenticated-orcid":false,"given":"Gamana","family":"Aragonda","sequence":"first","affiliation":[{"name":"New Jersey Institute of Technology, NEWARK, NJ, USA"}]},{"ORCID":"https:\/\/orcid.org\/0009-0008-2734-8935","authenticated-orcid":false,"given":"Deniz","family":"Najafi","sequence":"additional","affiliation":[{"name":"New Jersey Institute of Technology, NEWARK, NJ, USA"}]},{"ORCID":"https:\/\/orcid.org\/0009-0000-8659-2040","authenticated-orcid":false,"given":"Deepak","family":"Vungarala","sequence":"additional","affiliation":[{"name":"New Jersey Institute of Technology, NEWARK, NJ, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5105-3450","authenticated-orcid":false,"given":"Sepehr","family":"Tabrizchi","sequence":"additional","affiliation":[{"name":"University of Illinois Chicago, Chicago, Illinois, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0900-8768","authenticated-orcid":false,"given":"Arman","family":"Roohi","sequence":"additional","affiliation":[{"name":"University of Illinois Chicago, Chicago, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2289-6381","authenticated-orcid":false,"given":"Shaahin","family":"Angizi","sequence":"additional","affiliation":[{"name":"New Jersey Institute of Technology, NEWARK, NJ, USA"}]}],"member":"320","published-online":{"date-parts":[[2025,6,29]]},"reference":[{"key":"e_1_3_3_1_2_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS45731.2020.9181068"},{"key":"e_1_3_3_1_3_2","doi-asserted-by":"publisher","unstructured":"Emna Baccour et\u00a0al. 2022. Pervasive AI for IoT Applications: A Survey on Resource-Efficient Distributed Artificial Intelligence. IEEE Communications Surveys & Tutorials 24 4 (2022) 2366\u20132418. 10.1109\/COMST.2022.3200740","DOI":"10.1109\/COMST.2022.3200740"},{"key":"e_1_3_3_1_4_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00040"},{"key":"e_1_3_3_1_5_2","first-page":"1","volume-title":"Proceedings of the 55th Annual Design Automation Conference","author":"al. S.\u00a0Angizi et","year":"2018","unstructured":"S.\u00a0Angizi et al.2018. Cmp-pim: an energy-efficient comparator-based processing-in-memory neural network accelerator. In Proceedings of the 55th Annual Design Automation Conference. 1\u20136."},{"key":"e_1_3_3_1_6_2","first-page":"378","volume-title":"2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)","author":"al. S.\u00a0Angizi et","year":"2019","unstructured":"S.\u00a0Angizi et al.2019. GraphS: A graph processing accelerator leveraging SOT-MRAM. In 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 378\u2013383."},{"key":"e_1_3_3_1_7_2","doi-asserted-by":"crossref","unstructured":"S.\u00a0Angizi et al.2019. Mrima: An mram-based in-memory accelerator. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 39 5 (2019) 1123\u20131136.","DOI":"10.1109\/TCAD.2019.2907886"},{"key":"e_1_3_3_1_8_2","doi-asserted-by":"crossref","unstructured":"S.\u00a0Angizi et al.2021. MeF-RAM: A New Non-Volatile Cache Memory Based on Magneto-Electric FET. ACM TODAES 27 (2021) 1\u201318. doi: 10.1145\/3484222.","DOI":"10.1145\/3484222"},{"key":"e_1_3_3_1_9_2","doi-asserted-by":"crossref","unstructured":"X.\u00a0Dong et al.2012. Nvsim: A circuit-level performance energy and area model for emerging nonvolatile memory. IEEE TCAD 31 (2012) 994\u20131007. doi: 10.1109\/TCAD.2012.2185930.","DOI":"10.1109\/TCAD.2012.2185930"},{"key":"e_1_3_3_1_10_2","doi-asserted-by":"crossref","unstructured":"X.\u00a0Fong et al.2015. Spin-transfer torque devices for logic and memory: Prospects and perspectives. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 35 1 (2015) 1\u201322.","DOI":"10.1109\/TCAD.2015.2481793"},{"key":"e_1_3_3_1_11_2","doi-asserted-by":"crossref","unstructured":"Je-Min Hung et\u00a0al. 2021. Challenges and Trends of Nonvolatile In-Memory-Computation Circuits for AI Edge Devices. IEEE Open Journal of the Solid-State Circuits Society 1 (2021) 171\u2013183.","DOI":"10.1109\/OJSSCS.2021.3123287"},{"key":"e_1_3_3_1_12_2","doi-asserted-by":"publisher","unstructured":"Je-Min Hung et\u00a0al. 2023. 8-b Precision 8-Mb ReRAM Compute-in-Memory Macro Using Direct-Current-Free Time-Domain Readout Scheme for AI Edge Devices. IEEE Journal of Solid-State Circuits 58 1 (2023) 303\u2013315. 10.1109\/JSSC.2022.3200515","DOI":"10.1109\/JSSC.2022.3200515"},{"key":"e_1_3_3_1_13_2","doi-asserted-by":"crossref","unstructured":"Chuan-Jia Jhang et\u00a0al. 2021. Challenges and Trends of SRAM-Based Computing-In-Memory for AI Edge Devices. IEEE TCASI 68 5 (2021) 1773\u20131786.","DOI":"10.1109\/TCSI.2021.3064189"},{"key":"e_1_3_3_1_14_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED57927.2023.10129307"},{"key":"e_1_3_3_1_15_2","doi-asserted-by":"publisher","unstructured":"Sangjin Kim and Hoi-Jun Yoo. 2024. An Overview of Computing-in-Memory Circuits With DRAM and NVM. IEEE Transactions on Circuits and Systems II: Express Briefs 71 3 (2024) 1626\u20131631. 10.1109\/TCSII.2023.3333851","DOI":"10.1109\/TCSII.2023.3333851"},{"key":"e_1_3_3_1_16_2","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2898064"},{"key":"e_1_3_3_1_17_2","doi-asserted-by":"publisher","unstructured":"Yueting Li et\u00a0al. 2023. A Survey of MRAM-Centric Computing: From Near Memory to In Memory. IEEE Transactions on Emerging Topics in Computing 11 2 (2023) 318\u2013330. 10.1109\/TETC.2022.3214833","DOI":"10.1109\/TETC.2022.3214833"},{"key":"e_1_3_3_1_18_2","doi-asserted-by":"publisher","DOI":"10.1145\/3649476.3660361"},{"key":"e_1_3_3_1_19_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS48785.2022.9937586"},{"key":"e_1_3_3_1_20_2","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD51958.2021.9643526"},{"key":"e_1_3_3_1_21_2","doi-asserted-by":"publisher","unstructured":"Md. Maruf\u00a0Hossain Shuvo et\u00a0al. 2023. Efficient Acceleration of Deep Learning Inference on Resource-Constrained Edge Devices: A Review. Proc. IEEE 111 1 (2023) 42\u201391. 10.1109\/JPROC.2022.3226481","DOI":"10.1109\/JPROC.2022.3226481"},{"key":"e_1_3_3_1_22_2","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD57390.2023.10323763"},{"key":"e_1_3_3_1_23_2","doi-asserted-by":"crossref","unstructured":"De-Qi You et\u00a0al. 2024. An 8b-Precision 8-Mb STT-MRAM Near-Memory-Compute Macro Using Weight-Feature and Input-Sparsity Aware Schemes for Energy-Efficient Edge AI Devices. IEEE JxCDC 59 1 (2024) 219\u2013230.","DOI":"10.1109\/JSSC.2023.3324335"},{"key":"e_1_3_3_1_24_2","doi-asserted-by":"crossref","unstructured":"Ke Yu et\u00a0al. 2024. Trends and Challenges in Computing-in-Memory for Neural Network Model: A Review From Device Design to Application-Side Optimization. IEEE Access 12 (2024) 186679\u2013186702.","DOI":"10.1109\/ACCESS.2024.3511492"},{"key":"e_1_3_3_1_25_2","doi-asserted-by":"publisher","unstructured":"Mingyang Zhou et\u00a0al. 2023. Power-Aware Quantization in Analog In-Memory Computing With STT-MRAM Macro. IEEE Transactions on Magnetics 59 11 (2023) 1\u20135. 10.1109\/TMAG.2023.3286467","DOI":"10.1109\/TMAG.2023.3286467"}],"event":{"name":"GLSVLSI '25: Great Lakes Symposium on VLSI 2025","sponsor":["SIGDA ACM Special Interest Group on Design Automation"],"location":"New Orleans LA USA","acronym":"GLSVLSI '25"},"container-title":["Proceedings of the Great Lakes Symposium on VLSI 2025"],"original-title":[],"deposited":{"date-parts":[[2025,6,27]],"date-time":"2025-06-27T14:35:18Z","timestamp":1751034918000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3716368.3735277"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,6,29]]},"references-count":24,"alternative-id":["10.1145\/3716368.3735277","10.1145\/3716368"],"URL":"https:\/\/doi.org\/10.1145\/3716368.3735277","relation":{},"subject":[],"published":{"date-parts":[[2025,6,29]]},"assertion":[{"value":"2025-06-29","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}