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Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2025,5,31]]},"abstract":"<jats:p>Transformers have revolutionized deep learning and generative modeling, enabling advancements in natural language processing tasks. However, the size of transformer models is increasing continuously, driven by enhanced capabilities across various deep learning tasks. This trend of ever-increasing model size has given rise to new challenges in terms of memory and compute requirements. Conventional computing platforms, including GPUs, suffer from suboptimal performance due to the memory demands imposed by models with millions\/billions of parameters. The emerging chiplet-based platforms provide a new avenue for compute- and data-intensive machine learning applications enabled by a Network-on-Interposer (NoI). However, designing suitable hardware accelerators for executing Transformer inference workloads is challenging due to a wide variety of complex computing kernels in the Transformer architecture. In this article, we leverage chiplet-based heterogeneous integration to design a high-performance and energy-efficient multichiplet platform to accelerate transformer workloads. We demonstrate that the proposed NoI architecture caters to the data access patterns inherent in a transformer model. The optimized placement of the chiplets and the associated NoI links and routers enable superior performance compared to the state-of-the-art hardware accelerators. The proposed NoI-based architecture demonstrates scalability across varying transformer models and improves latency and energy efficiency by up to 11.8\u00d7 and 2.36\u00d7, respectively when compared with the existing state-of-the-art architecture HAIMA.<\/jats:p>","DOI":"10.1145\/3718487","type":"journal-article","created":{"date-parts":[[2025,2,19]],"date-time":"2025-02-19T11:19:52Z","timestamp":1739963992000},"page":"1-24","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":10,"title":["A Heterogeneous Chiplet Architecture for Accelerating End-to-End Transformer Models"],"prefix":"10.1145","volume":"30","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-0334-4269","authenticated-orcid":false,"given":"Harsh","family":"Sharma","sequence":"first","affiliation":[{"name":"Washington State University, Pullman, United States"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0000-0422-3365","authenticated-orcid":false,"given":"Pratyush","family":"Dhingra","sequence":"additional","affiliation":[{"name":"Washington State University, Pullman, United States"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3848-5301","authenticated-orcid":false,"given":"Jana","family":"Doppa","sequence":"additional","affiliation":[{"name":"Washington State University, Pullman, United States"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5045-5535","authenticated-orcid":false,"given":"Umit","family":"Ogras","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, University of Wisconsin-Madison, Madison, United States"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5930-8531","authenticated-orcid":false,"given":"Partha Pratim","family":"Pande","sequence":"additional","affiliation":[{"name":"Washington State University, Pullman, United States"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2025,4,12]]},"reference":[{"key":"e_1_3_1_2_2","article-title":"ReTransformer: ReRAM-based processing-in-memory architecture for transformer acceleration","author":"Yang X.","year":"2020","unstructured":"X. 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