{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,2]],"date-time":"2025-08-02T16:26:35Z","timestamp":1754151995171,"version":"3.41.2"},"publisher-location":"New York, NY, USA","reference-count":39,"publisher":"ACM","funder":[{"name":"Strategic Priority Research Program of Chinese Academy of Sciences","award":["XDB0660202"],"award-info":[{"award-number":["XDB0660202"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2025,5,28]]},"DOI":"10.1145\/3719276.3725171","type":"proceedings-article","created":{"date-parts":[[2025,7,4]],"date-time":"2025-07-04T05:00:46Z","timestamp":1751605246000},"page":"88-97","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["AdaTP: Enhancing Temporal Prefetching with Adaptive Metadata Filtering"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0009-0003-6118-3541","authenticated-orcid":false,"given":"Junliang","family":"Wu","sequence":"first","affiliation":[{"name":"State Key Lab of Processors, Institute of Computing Technology, CAS, Beijing, China and University of Chinese Academy of Sciences, Beijing, China"}]},{"ORCID":"https:\/\/orcid.org\/0009-0005-3118-8477","authenticated-orcid":false,"given":"Feng","family":"Xue","sequence":"additional","affiliation":[{"name":"State Key Lab of Processors, Institute of Computing Technology, CAS, Beijing, China and University of Chinese Academy of Sciences, Beijing, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0430-3669","authenticated-orcid":false,"given":"Fuxin","family":"Zhang","sequence":"additional","affiliation":[{"name":"State Key Lab of Processors, Institute of Computing Technology, CAS, Beijing, China"}]}],"member":"320","published-online":{"date-parts":[[2025,7,4]]},"reference":[{"volume-title":"The 2nd Data Prefetching Championship","year":"2015","key":"e_1_3_3_2_2_2","unstructured":"2015. The 2nd Data Prefetching Championship. https:\/\/comparch-conf.gatech.edu\/dpc2\/"},{"volume-title":"The 3rd Data Prefetching Championship","year":"2019","key":"e_1_3_3_2_3_2","unstructured":"2019. The 3rd Data Prefetching Championship. https:\/\/dpc3.compas.cs.stonybrook.edu\/"},{"key":"e_1_3_3_2_4_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA59077.2024.00090"},{"key":"e_1_3_3_2_5_2","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2014.6974670"},{"key":"e_1_3_3_2_6_2","doi-asserted-by":"publisher","DOI":"10.1145\/125826.125932"},{"key":"e_1_3_3_2_7_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2019.00053"},{"key":"e_1_3_3_2_8_2","doi-asserted-by":"publisher","DOI":"10.1145\/3466752.3480114"},{"key":"e_1_3_3_2_9_2","volume-title":"SPEC CPU2006","author":"Corporation Standard Performance\u00a0Evaluation","year":"2006","unstructured":"Standard Performance\u00a0Evaluation Corporation. 2006. SPEC CPU2006. http:\/\/www.spec.org\/cpu2006"},{"key":"e_1_3_3_2_10_2","volume-title":"SPEC CPU2017","author":"Corporation Standard Performance\u00a0Evaluation","year":"2017","unstructured":"Standard Performance\u00a0Evaluation Corporation. 2017. SPEC CPU2017. http:\/\/www.spec.org\/cpu2017"},{"key":"e_1_3_3_2_11_2","doi-asserted-by":"crossref","unstructured":"Fredrik Dahlgren Michel Dubois and Per Stenstr\u00f6m. 1995. Sequential Hardware Prefetching in Shared-Memory Multiprocessors. IEEE Trans. Parallel Distrib. Syst. 6 7 (July 1995) 733\u2013746. https:\/\/doi.org\/10.1109\/71.395402","DOI":"10.1109\/71.395402"},{"key":"e_1_3_3_2_12_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.1995.386554"},{"key":"e_1_3_3_2_13_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA59077.2024.00088"},{"key":"e_1_3_3_2_14_2","unstructured":"Nathan Gober Gino Chacon Lei Wang Paul\u00a0V. Gratz Daniel\u00a0A. Jimenez Elvira Teran Seth Pugsley and Jinchun Kim. 2022. The Championship Simulator: Architectural Simulation for Education and Competition. (2022). https:\/\/doi.org\/10.48550\/arXiv.2210.14324"},{"key":"e_1_3_3_2_15_2","doi-asserted-by":"crossref","unstructured":"Muhammad Hassan Chang\u00a0Hyun Park and David Black-Schaffer. 2021. A Reusable Characterization of the Memory System Behavior of SPEC2017 and SPEC2006. ACM Trans. Archit. Code Optim. 18 2 Article 24 (March 2021) 20\u00a0pages. https:\/\/doi.org\/10.1145\/3446200","DOI":"10.1145\/3446200"},{"key":"e_1_3_3_2_16_2","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540730"},{"key":"e_1_3_3_2_17_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2016.17"},{"key":"e_1_3_3_2_18_2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO56248.2022.00071"},{"key":"e_1_3_3_2_19_2","doi-asserted-by":"crossref","unstructured":"D. Joseph and D. Grunwald. 1999. Prefetching using Markov predictors. IEEE Trans. Comput. 48 2 (1999) 121\u2013133. https:\/\/doi.org\/10.1109\/12.752653","DOI":"10.1109\/12.752653"},{"key":"e_1_3_3_2_20_2","doi-asserted-by":"publisher","DOI":"10.1145\/325164.325162"},{"key":"e_1_3_3_2_21_2","doi-asserted-by":"crossref","unstructured":"Mazen Kharbutli and Rami Sheikh. 2014. LACS: A Locality-Aware Cost-Sensitive Cache Replacement Algorithm. IEEE Trans. Comput. 63 8 (2014) 1975\u20131987. https:\/\/doi.org\/10.1109\/TC.2013.61","DOI":"10.1109\/TC.2013.61"},{"key":"e_1_3_3_2_22_2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2016.7783763"},{"key":"e_1_3_3_2_23_2","doi-asserted-by":"publisher","DOI":"10.1145\/3503222.3507745"},{"key":"e_1_3_3_2_24_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA59077.2024.00012"},{"key":"e_1_3_3_2_25_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2016.7446087"},{"key":"e_1_3_3_2_26_2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO56248.2022.00072"},{"key":"e_1_3_3_2_27_2","doi-asserted-by":"crossref","unstructured":"K.J. Nesbit and J.E. Smith. 2005. Data cache prefetching using a global history buffer. IEEE Micro 25 1 (2005) 90\u201397. https:\/\/doi.org\/10.1109\/MM.2005.6","DOI":"10.1109\/MM.2005.6"},{"key":"e_1_3_3_2_28_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA45697.2020.00021"},{"key":"e_1_3_3_2_29_2","doi-asserted-by":"publisher","DOI":"10.1145\/3613424.3614245"},{"key":"e_1_3_3_2_30_2","doi-asserted-by":"publisher","DOI":"10.1109\/HCS52781.2021.9567483"},{"key":"e_1_3_3_2_31_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835971"},{"key":"e_1_3_3_2_32_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2006.5"},{"key":"e_1_3_3_2_33_2","volume-title":"5th JILP Workshop on Computer Architecture Competitions (JWAC-5): Championship Branch Prediction (CBP-5)","author":"Seznec Andr\u00e9","year":"2016","unstructured":"Andr\u00e9 Seznec. 2016. Tage-sc-l branch predictors again. In 5th JILP Workshop on Computer Architecture Competitions (JWAC-5): Championship Branch Prediction (CBP-5)."},{"key":"e_1_3_3_2_34_2","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830793"},{"key":"e_1_3_3_2_35_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2006.38"},{"key":"e_1_3_3_2_36_2","doi-asserted-by":"crossref","unstructured":"Jonathan Woodruff Alexandre Joannou Hongyan Xia Anthony Fox Robert\u00a0M Norton David Chisnall Brooks Davis Khilan Gudka Nathaniel\u00a0W Filardo A\u00a0Theodore Markettos et\u00a0al. 2019. Cheri concentrate: Practical compressed capabilities. IEEE Trans. Comput. 68 10 (2019) 1455\u20131469.","DOI":"10.1109\/TC.2019.2914037"},{"key":"e_1_3_3_2_37_2","doi-asserted-by":"crossref","unstructured":"Hao Wu Krishnendra Nathella Matthew Pabst Dam Sunwoo Akanksha Jain and Calvin Lin. 2022. Practical Temporal Prefetching With Compressed On-Chip Metadata. IEEE Trans. Comput. 71 11 (2022) 2858\u20132871. https:\/\/doi.org\/10.1109\/TC.2021.3065909","DOI":"10.1109\/TC.2021.3065909"},{"key":"e_1_3_3_2_38_2","doi-asserted-by":"publisher","DOI":"10.1145\/3352460.3358300"},{"key":"e_1_3_3_2_39_2","doi-asserted-by":"publisher","DOI":"10.1145\/3307650.3322225"},{"key":"e_1_3_3_2_40_2","doi-asserted-by":"crossref","unstructured":"Feng Xue Chenji Han Xinyu Li Junliang Wu Tingting Zhang Tianyi Liu Yifan Hao Zidong Du Qi Guo and Fuxin Zhang. 2024. Tyche: An Efficient and General Prefetcher for Indirect Memory Accesses. ACM Trans. Archit. Code Optim. 21 2 Article 30 (March 2024) 26\u00a0pages. https:\/\/doi.org\/10.1145\/3641853","DOI":"10.1145\/3641853"}],"event":{"name":"CF '25: 22nd ACM International Conference on Computing Frontiers","sponsor":["SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing"],"location":"Cagliari Italy","acronym":"CF '25"},"container-title":["Proceedings of the 22nd ACM International Conference on Computing Frontiers"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3719276.3725171","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,7,21]],"date-time":"2025-07-21T09:49:39Z","timestamp":1753091379000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3719276.3725171"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,5,28]]},"references-count":39,"alternative-id":["10.1145\/3719276.3725171","10.1145\/3719276"],"URL":"https:\/\/doi.org\/10.1145\/3719276.3725171","relation":{},"subject":[],"published":{"date-parts":[[2025,5,28]]},"assertion":[{"value":"2025-07-04","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}