{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,2]],"date-time":"2025-08-02T16:26:30Z","timestamp":1754151990299,"version":"3.41.2"},"publisher-location":"New York, NY, USA","reference-count":34,"publisher":"ACM","content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2025,5,28]]},"DOI":"10.1145\/3719276.3725181","type":"proceedings-article","created":{"date-parts":[[2025,7,4]],"date-time":"2025-07-04T05:00:46Z","timestamp":1751605246000},"page":"3-11","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Register Dispersion: Reducing the Footprint of the Vector Register File in Vector Engines of Low-Cost RISC-V CPUs"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0009-0009-0123-5737","authenticated-orcid":false,"given":"Vasileios","family":"Titopoulos","sequence":"first","affiliation":[{"name":"Electrical and Computer Engineering Democritus University of Thrace, Xanthi, Greece"}]},{"ORCID":"https:\/\/orcid.org\/0009-0005-8160-1389","authenticated-orcid":false,"given":"George","family":"Alexakis","sequence":"additional","affiliation":[{"name":"Electrical and Computer Engineering Democritus University of Thrace, Xanthi, Greece"}]},{"ORCID":"https:\/\/orcid.org\/0009-0002-7680-1982","authenticated-orcid":false,"given":"Kosmas","family":"Alexandridis","sequence":"additional","affiliation":[{"name":"Electrical and Computer Engineering Democritus University of Thrace, Xanthi, Greece"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6389-6068","authenticated-orcid":false,"given":"Chrysostomos","family":"Nicopoulos","sequence":"additional","affiliation":[{"name":"Electrical and Computer Engineering University of Cyprus, Nicosia, Cyprus"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3688-7865","authenticated-orcid":false,"given":"Giorgos","family":"Dimitrakopoulos","sequence":"additional","affiliation":[{"name":"Electrical and Computer Engineering Democritus University of Thrace, Xanthi, Greece"}]}],"member":"320","published-online":{"date-parts":[[2025,7,4]]},"reference":[{"key":"e_1_3_3_1_2_2","doi-asserted-by":"publisher","DOI":"10.1145\/3589236.3589245"},{"key":"e_1_3_3_1_3_2","doi-asserted-by":"publisher","DOI":"10.1109\/CADS.2017.8310675"},{"key":"e_1_3_3_1_4_2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2001.991122"},{"key":"e_1_3_3_1_5_2","doi-asserted-by":"crossref","unstructured":"N. Bleier A. Wezelis L. Varshney and R. Kumar. 2024. Programmable Olfactory Computing. IEEE Micro 44 04 (2024) 88\u201396.","DOI":"10.1109\/MM.2024.3409619"},{"key":"e_1_3_3_1_6_2","doi-asserted-by":"publisher","DOI":"10.23919\/DATE54114.2022.9774730"},{"key":"e_1_3_3_1_7_2","doi-asserted-by":"crossref","unstructured":"M. Cavalcante F. Schuiki F. Zaruba M. Schaffner and L. Benini. 2020. Ara: A 1-GHz+ Scalable and Energy-Efficient RISC-V Vector Processor With Multiprecision Floating-Point Support in 22-nm FD-SOI. IEEE Trans. on VLSI Systems 28 2 (feb 2020) 530\u2013543.","DOI":"10.1109\/TVLSI.2019.2950087"},{"key":"e_1_3_3_1_8_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA45697.2020.00016"},{"key":"e_1_3_3_1_9_2","unstructured":"Codasip. 2022. L31 RISC-V embedded processor. Retrieved January 25 2025 from https:\/\/codasip.com\/products\/low-power-embedded-risc-v-processors\/l31"},{"key":"e_1_3_3_1_10_2","doi-asserted-by":"publisher","DOI":"10.1145\/2934495.2934497"},{"key":"e_1_3_3_1_11_2","unstructured":"Jacobs Eino Utyansky Dmitry Hassan Muhammad and Thomas Roecker. 2024. RISC-V V Vector Extension (RVV) with reduced number of vector registers. (2024). arXiv:https:\/\/arXiv.org\/abs\/2410.08396"},{"key":"e_1_3_3_1_12_2","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2016.90"},{"key":"e_1_3_3_1_13_2","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2017.243"},{"key":"e_1_3_3_1_14_2","unstructured":"Devlin Jacob Chang Ming-Wei Lee Kenton and Toutanova Kristina. 2019. BERT: Pre-training of Deep Bidirectional Transformers for Language Understanding. (2019). arXiv:https:\/\/arXiv.org\/abs\/1810.04805"},{"key":"e_1_3_3_1_15_2","doi-asserted-by":"publisher","DOI":"10.1109\/FDL50818.2020.9232940"},{"key":"e_1_3_3_1_16_2","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859664"},{"key":"e_1_3_3_1_17_2","doi-asserted-by":"crossref","unstructured":"C.E. Kozyrakis and D.A. Patterson. 2003. Scalable vector processors for embedded systems. IEEE Micro 23 6 (2003) 36\u201345.","DOI":"10.1109\/MM.2003.1261385"},{"key":"e_1_3_3_1_18_2","doi-asserted-by":"crossref","unstructured":"Cristobal\u00a0Ramirez Lazo Enrico Reggiani Carlos\u00a0Rojas Morales Roger Figueras\u00a0Bague Luis\u00a0A. Villa\u00a0Vargas Marco\u00a0A. Ramirez\u00a0Salinas Mateo\u00a0Valero Cortes Osman Sabri\u00a0Unsal and Adrian Cristal. 2021. Adaptable Register File Organization for Vector Processors. IEEE Inter. Symp. on High-Performance Computer Architecture (HPCA) (2021) 786\u2013799.","DOI":"10.1109\/HPCA53966.2022.00063"},{"key":"e_1_3_3_1_19_2","doi-asserted-by":"crossref","unstructured":"Shih\u00a0Hsiung Lee. 2022. Real-time edge computing on multi-processes and multi-threading architectures for deep learning applications. Microprocessors and Microsystems 92 (2022) 104554.","DOI":"10.1016\/j.micpro.2022.104554"},{"key":"e_1_3_3_1_20_2","doi-asserted-by":"crossref","unstructured":"Malith Maheepala Matthew\u00a0A. Joordens and Abbas\u00a0Z. Kouzani. 2021. Low Power Processors and Image Sensors for Vision-Based IoT Devices: A Review. IEEE Sensors Journal 21 2 (2021) 1172\u20131186.","DOI":"10.1109\/JSEN.2020.3015932"},{"key":"e_1_3_3_1_21_2","doi-asserted-by":"crossref","unstructured":"Francesco Minervini Oscar Palomar Osman Unsal Enrico Reggiani Josue Quiroga Joan Marimon Carlos Rojas Roger Figueras Abraham Ruiz Alberto Gonzalez Jonnatan Mendoza Ivan Vargas C\u00e9sar Hernandez Joan Cabre Lina Khoirunisya Mustapha Bouhali Julian Pavon Francesc Moll Mauro Olivieri Mario Kovac Mate Kovac Leon Dragic Mateo Valero and Adrian Cristal. 2023. Vitruvius+: an area-efficient RISC-V decoupled vector coprocessor for high performance computing applications. ACM Trans. on Arch. and Code Optim. (TACO) 20 2 (2023) 1\u201325.","DOI":"10.1145\/3575861"},{"key":"e_1_3_3_1_22_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS45731.2020.9181071"},{"key":"e_1_3_3_1_23_2","doi-asserted-by":"crossref","unstructured":"Matteo Perotti Matheus Cavalcante Renzo Andri Lukas Cavigelli and Luca Benini. 2024. Ara2: Exploring Single- and Multi-Core Vector Processing With an Efficient RVV 1.0 Compliant Open-Source Processor. IEEE Trans. on Computers 73 7 (2024) 1822\u20131836.","DOI":"10.1109\/TC.2024.3388896"},{"key":"e_1_3_3_1_24_2","doi-asserted-by":"crossref","unstructured":"Matteo Perotti Samuel Riedel Matheus Cavalcante and Luca Benini. 2025. Spatz: Clustering Compact RISC-V-Based Vector Units to Maximize Computing Efficiency. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems preprint (2025).","DOI":"10.1109\/TCAD.2025.3528349"},{"key":"e_1_3_3_1_25_2","first-page":"1:1\u20131:18","volume-title":"33rd Euromicro Conference on Real-Time Systems (ECRTS)","author":"Platzer Michael","year":"2021","unstructured":"Michael Platzer and Peter Puschner. 2021. Vicuna: A Timing-Predictable RISC-V Vector Coprocessor for Scalable Parallel Computation. In 33rd Euromicro Conference on Real-Time Systems (ECRTS). 1:1\u20131:18."},{"key":"e_1_3_3_1_26_2","doi-asserted-by":"crossref","unstructured":"N.\u00a0K. Purayil Matteo Perotti Tim Fischer and Luca Benini. 2025. AraXL: A Physically Scalable Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors. (2025). arXiv:https:\/\/arXiv.org\/abs\/2501.10301","DOI":"10.23919\/DATE64628.2025.10992880"},{"key":"e_1_3_3_1_27_2","doi-asserted-by":"crossref","unstructured":"Crist\u00f3bal Ram\u00edrez C\u00e9sar-Alejandro Hern\u00e1ndez-Calder\u00f3n Oscar Palomar Osman\u00a0Sabri Unsal Marco\u00a0Antonio Ram\u00edrez and Adri\u00e1n Cristal. 2020. A RISC-V Simulator and Benchmark Suite for Designing and Evaluating Vector Architectures. ACM Transactions on Architecture and Code Optimization (TACO) 17 4 (2020) 1 \u2013 30.","DOI":"10.1145\/3422667"},{"key":"e_1_3_3_1_28_2","doi-asserted-by":"publisher","DOI":"10.1145\/2903150.2903485"},{"key":"e_1_3_3_1_29_2","unstructured":"STMicroelectronics. 2023. STM32 Toolchain Specifications. Retrieved September 17 2024 from https:\/\/www.st.com\/en\/microcontrollers-microprocessors\/stm32h743ii.html"},{"key":"e_1_3_3_1_30_2","unstructured":"Espressif Systems. 2024. ESP32 - Technical Reference Manual. Espressif whitepaper."},{"key":"e_1_3_3_1_31_2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO56248.2022.00025"},{"key":"e_1_3_3_1_32_2","unstructured":"Dao Tri. 2023. FlashAttention-2: Faster Attention with Better Parallelism and Work Partitioning. (2023). arXiv:https:\/\/arXiv.org\/abs\/2307.08691"},{"key":"e_1_3_3_1_33_2","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2017.7995254"},{"key":"e_1_3_3_1_34_2","unstructured":"J. Yiu. 2020. Introduction to the ARM Cortex-M55 Processor. ARM whitepaper."},{"key":"e_1_3_3_1_35_2","unstructured":"Jerry Zhao Daniel Grubb Miles Rusch Tianrui Wei Kevin Anderson Borivoje Nikolic and Krste Asanovic. 2024. Instruction Scheduling in the Saturn Vector Unit. (2024). arXiv:https:\/\/arXiv.org\/abs\/2412.00997"}],"event":{"name":"CF '25: 22nd ACM International Conference on Computing Frontiers","sponsor":["SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing"],"location":"Cagliari Italy","acronym":"CF '25"},"container-title":["Proceedings of the 22nd ACM International Conference on Computing Frontiers"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3719276.3725181","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,7,21]],"date-time":"2025-07-21T09:48:47Z","timestamp":1753091327000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3719276.3725181"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,5,28]]},"references-count":34,"alternative-id":["10.1145\/3719276.3725181","10.1145\/3719276"],"URL":"https:\/\/doi.org\/10.1145\/3719276.3725181","relation":{},"subject":[],"published":{"date-parts":[[2025,5,28]]},"assertion":[{"value":"2025-07-04","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}