{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,12]],"date-time":"2026-02-12T11:23:59Z","timestamp":1770895439847,"version":"3.50.1"},"reference-count":30,"publisher":"Association for Computing Machinery (ACM)","issue":"3","funder":[{"name":"Research Grants Council of Hong Kong SAR","award":["RFS2425-4S02, CUHK14211824"],"award-info":[{"award-number":["RFS2425-4S02, CUHK14211824"]}]},{"name":"The Natural Science Foundation of Beijing, China","award":["Z230002"],"award-info":[{"award-number":["Z230002"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2026,5,31]]},"abstract":"<jats:p>\n                    Face-to-face (F2F) stacked three-dimensional (3D) IC is a promising alternative for scaling beyond Moore\u2019s Law. In F2F 3D ICs, dies are connected through bonding terminals whose positions can significantly impact routing performance. Further, there exists resource competition among all the 3D nets due to the constrained bonding terminal number. In advanced technology nodes, traditional bonding terminal planning may also introduce legality challenges of bonding terminals, as the metal pitches can be much smaller than the sizes of bonding terminals. Previous works attempt to insert bonding terminals automatically using existing 2D commercial P&amp;R tools and then consider interdie connection legality, but they fail to take the legality and routing performance into account simultaneously. In this article, we provide a novel bonding terminal assignment formulation for effective routing-aware bonding terminal planning. We explore the generalized assignment formulation and provide the routability guidance in our hybrid bonding terminal assignment problem. Our framework,\n                    <jats:italic toggle=\"yes\">BTAssign<\/jats:italic>\n                    , offers a strict legality guarantee and an iterative solution. We provide two versions of the BTAssign framework, BTAssign-WL\u00a0[\n                    <jats:xref ref-type=\"bibr\">1<\/jats:xref>\n                    ] and BTAssign-R, which BTAssign-R extends BTAssign-WL\u00a0[\n                    <jats:xref ref-type=\"bibr\">1<\/jats:xref>\n                    ] by considering routability. The experiments are conducted on 18 open source designs with various 3D net densities and the most advanced bonding scale. The results reveal that all the testing cases with different partitioning and placement strategies could gain benefits from our BTAssign framework.\n                  <\/jats:p>","DOI":"10.1145\/3721131","type":"journal-article","created":{"date-parts":[[2025,3,6]],"date-time":"2025-03-06T06:31:57Z","timestamp":1741242717000},"page":"1-20","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Routing-aware Legal Hybrid Bonding Terminal Assignment for 3D Face-to-Face Stacked ICs"],"prefix":"10.1145","volume":"31","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-2454-5561","authenticated-orcid":false,"given":"Siting","family":"Liu","sequence":"first","affiliation":[{"name":"Computer Science and Engineering, The Chinese University of Hong Kong","place":["Hong Kong, Hong Kong"]}]},{"ORCID":"https:\/\/orcid.org\/0009-0008-2643-5092","authenticated-orcid":false,"given":"Jieya","family":"Zhou","sequence":"additional","affiliation":[{"name":"Computer Science, Chinese University of Hong Kong Chung Chi College","place":["Hong Kong, Hong Kong"]}]},{"ORCID":"https:\/\/orcid.org\/0009-0006-0228-1960","authenticated-orcid":false,"given":"Jiaxi","family":"Jiang","sequence":"additional","affiliation":[{"name":"Computer Science and Engineering, The Chinese University of Hong Kong Faculty of Engineering","place":["Hong Kong, Hong Kong"]}]},{"ORCID":"https:\/\/orcid.org\/0009-0009-4909-6588","authenticated-orcid":false,"given":"Zhuolun","family":"He","sequence":"additional","affiliation":[{"name":"The Chinese University of Hong Kong","place":["Hong Kong, Hong Kong"]}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1694-5047","authenticated-orcid":false,"given":"Ziyi","family":"Wang","sequence":"additional","affiliation":[{"name":"Computer Science and Engineering, The Chinese University of Hong Kong","place":["Hong Kong, Hong Kong"]}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0977-2774","authenticated-orcid":false,"given":"Yibo","family":"Lin","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Peking University","place":["Beijing, China"]}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6406-4810","authenticated-orcid":false,"given":"Bei","family":"Yu","sequence":"additional","affiliation":[{"name":"CSE, The Chinese University of Hong Kong","place":["Hong Kong, Hong Kong"]}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8274-9688","authenticated-orcid":false,"given":"Martin","family":"Wong","sequence":"additional","affiliation":[{"name":"Hong Kong Baptist University","place":["Hong Kong, Hong Kong"]}]}],"member":"320","published-online":{"date-parts":[[2026,2,11]]},"reference":[{"key":"e_1_3_1_2_2","doi-asserted-by":"publisher","DOI":"10.1145\/3626184.3633322"},{"key":"e_1_3_1_3_2","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2008.2007462"},{"key":"e_1_3_1_4_2","doi-asserted-by":"publisher","DOI":"10.1109\/IITC.2014.6831837"},{"key":"e_1_3_1_5_2","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18074.2021.9586246"},{"key":"e_1_3_1_6_2","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2008.4549988"},{"key":"e_1_3_1_7_2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2013.192"},{"key":"e_1_3_1_8_2","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM19573.2019.8993637"},{"key":"e_1_3_1_9_2","unstructured":"AMD 3D V-Cache Ryzen Chiplets. n.d. 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