{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,24]],"date-time":"2025-10-24T08:34:17Z","timestamp":1761294857502,"version":"3.44.0"},"publisher-location":"New York, NY, USA","reference-count":41,"publisher":"ACM","content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2025,6,8]]},"DOI":"10.1145\/3721145.3729513","type":"proceedings-article","created":{"date-parts":[[2025,8,22]],"date-time":"2025-08-22T12:57:17Z","timestamp":1755867437000},"page":"1176-1189","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["A Cost-Effective Dueling Framework for Set-Associative Cache Indexing"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-1746-6355","authenticated-orcid":false,"given":"Kevin","family":"Weston","sequence":"first","affiliation":[{"name":"Texas A&M University, College Station, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8656-4848","authenticated-orcid":false,"given":"Vahid","family":"Janfaza","sequence":"additional","affiliation":[{"name":"Texas A&M University, College Station, USA"}]},{"ORCID":"https:\/\/orcid.org\/0009-0009-3657-7139","authenticated-orcid":false,"given":"Avery","family":"Johnson","sequence":"additional","affiliation":[{"name":"Texas A&M University, College Station, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8145-815X","authenticated-orcid":false,"given":"Abdullah","family":"Muzahid","sequence":"additional","affiliation":[{"name":"Texas A&M University, College Station, USA"}]}],"member":"320","published-online":{"date-parts":[[2025,8,22]]},"reference":[{"key":"e_1_3_3_1_2_2","doi-asserted-by":"crossref","unstructured":"Anant Agarwal John Hennessy and Mark Horowitz. 1988. Cache Performance of Operating System and Multiprogramming Workloads. ACM Trans. Comput. Syst. 6 (nov 1988) 393\u2013431.","DOI":"10.1145\/48012.48037"},{"key":"e_1_3_3_1_3_2","doi-asserted-by":"publisher","DOI":"10.1145\/165123.165153"},{"key":"e_1_3_3_1_4_2","volume-title":"arXiv","author":"Beamer Scott","year":"2017","unstructured":"Scott Beamer, Krste Asanovi\u0107, and David Patterson. 2017. The GAP Benchmark Suite. In arXiv. arXiv:https:\/\/arXiv.org\/abs\/1508.03619"},{"key":"e_1_3_3_1_5_2","doi-asserted-by":"publisher","DOI":"10.1145\/3307650.3322207"},{"key":"e_1_3_3_1_6_2","doi-asserted-by":"publisher","DOI":"10.1145\/223982.224437"},{"key":"e_1_3_3_1_7_2","doi-asserted-by":"crossref","unstructured":"J.Lawrence Carter and Mark\u00a0N. Wegman. 1979. Universal classes of hash functions. J. Comput. System Sci. 18 2 (1979) 143\u2013154. https:\/\/doi.org\/10.1016\/0022-0000(79)90044-8","DOI":"10.1016\/0022-0000(79)90044-8"},{"key":"e_1_3_3_1_8_2","volume-title":"The 2nd Cache Replacement Championship","year":"2017","unstructured":"CRC-2. 2017. The 2nd Cache Replacement Championship. http:\/\/crc2.ece.tamu.edu"},{"key":"e_1_3_3_1_9_2","volume-title":"The 1st Championship Value Prediction","year":"2018","unstructured":"CVP-1. 2018. The 1st Championship Value Prediction. https:\/\/microarch.org\/cvp1\/"},{"key":"e_1_3_3_1_10_2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.13"},{"key":"e_1_3_3_1_11_2","volume-title":"The 3rd Data Prefetching Championship","year":"2019","unstructured":"DPC-3. 2019. The 3rd Data Prefetching Championship. https:\/\/dpc3.compas.cs.stonybrook.edu"},{"key":"e_1_3_3_1_12_2","doi-asserted-by":"publisher","DOI":"10.1145\/263580.263599"},{"key":"e_1_3_3_1_13_2","volume-title":"Computer Architecture, Sixth Edition: A Quantitative Approach (6th ed.)","author":"Hennessy John\u00a0L.","year":"2017","unstructured":"John\u00a0L. Hennessy and David\u00a0A. Patterson. 2017. Computer Architecture, Sixth Edition: A Quantitative Approach (6th ed.). Morgan Kaufmann Publishers Inc., San Francisco, CA, USA."},{"key":"e_1_3_3_1_14_2","volume-title":"An integrated cache and memory access time, cycle time, area, leakage, and dynamic power model","unstructured":"HP-Labs. [n. d.]. An integrated cache and memory access time, cycle time, area, leakage, and dynamic power model. https:\/\/www.hpl.hp.com\/research\/cacti"},{"key":"e_1_3_3_1_15_2","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2015.56"},{"key":"e_1_3_3_1_16_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2016.17"},{"key":"e_1_3_3_1_17_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00020"},{"key":"e_1_3_3_1_18_2","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815971"},{"key":"e_1_3_3_1_19_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2004.10015"},{"key":"e_1_3_3_1_20_2","doi-asserted-by":"publisher","DOI":"10.5555\/3195638.3195711"},{"key":"e_1_3_3_1_21_2","unstructured":"Jinchun Kim Elvira Teran Paul\u00a0V. Gratz Daniel\u00a0A. Jim\u00e9nez Seth\u00a0H. Pugsley and Chris Wilkerson. 2017. Kill the Program Counter: Reconstructing Program Behavior in the Processor Cache Hierarchy. ASPLOS (2017)."},{"key":"e_1_3_3_1_22_2","doi-asserted-by":"publisher","DOI":"10.1145\/3320269.3384746"},{"key":"e_1_3_3_1_23_2","volume-title":"UltraSPARC T2 supplement to the UltraSPARC architecture 2007","author":"Microsystems Sun","year":"2007","unstructured":"Sun Microsystems. 2007. UltraSPARC T2 supplement to the UltraSPARC architecture 2007. Technical Report."},{"key":"e_1_3_3_1_24_2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO56248.2022.00072"},{"key":"e_1_3_3_1_25_2","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250709"},{"key":"e_1_3_3_1_26_2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2018.00068"},{"key":"e_1_3_3_1_27_2","doi-asserted-by":"crossref","unstructured":"B.\u00a0Ramakrishna Rau. 1991. Pseudo-Randomly Interleaved Memory. SIGARCH Comput. Archit. News 19 3 (apr 1991) 74\u201383. https:\/\/doi.org\/10.1145\/115953.115961","DOI":"10.1145\/115953.115961"},{"key":"e_1_3_3_1_28_2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.20"},{"key":"e_1_3_3_1_29_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA51647.2021.00033"},{"key":"e_1_3_3_1_30_2","doi-asserted-by":"crossref","unstructured":"Andr\u00e9 Seznec. 1993. A case for two-way skewed-associative caches. ACM SIGARCH computer architecture news 21 2 (1993) 169\u2013178.","DOI":"10.1145\/173682.165152"},{"key":"e_1_3_3_1_31_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA53966.2022.00048"},{"key":"e_1_3_3_1_32_2","doi-asserted-by":"publisher","DOI":"10.1145\/3352460.3358319"},{"key":"e_1_3_3_1_33_2","doi-asserted-by":"publisher","DOI":"10.1145\/3445814.3446752"},{"key":"e_1_3_3_1_34_2","doi-asserted-by":"crossref","unstructured":"H.S. Stone. 1971. Parallel Processing with the Perfect Shuffle. IEEE Trans. Comput. C-20 2 (1971) 153\u2013161.","DOI":"10.1109\/T-C.1971.223205"},{"key":"e_1_3_3_1_35_2","unstructured":"Synopsis. [n. d.]. Synopsys Design Compiler NXT. https:\/\/www.synopsys.com\/implementation-and-signoff\/rtl-synthesis-test\/design-compiler-graphical.html."},{"key":"e_1_3_3_1_36_2","volume-title":"ISCA 2019","author":"Tarsa Stephen\u00a0J.","unstructured":"Stephen\u00a0J. Tarsa, Rangeen Basu\u00a0Roy Chowdhury, Julien Sebot, Gautham Chinya, Jayesh Gaur, Karthik Sankaranarayanan, Chit-Kwan Lin, Robert Chappell, Ronak Singhal, and Hong Wang. [n. d.]. Post-Silicon CPU Adaptation Made Practical Using Machine Learning. In ISCA 2019."},{"key":"e_1_3_3_1_37_2","doi-asserted-by":"publisher","DOI":"10.5555\/266800.266808"},{"key":"e_1_3_3_1_38_2","volume-title":"PHYSOR 2014 - The Role of Reactor Physics toward a Sustainable Future","author":"Tramm John","unstructured":"John Tramm, Andrew Siegel, Tanzima Islam, and Martin Schulz. [n. d.]. XSBench - The development and verification of a performance abstraction for Monte Carlo reactor analysis. In PHYSOR 2014 - The Role of Reactor Physics toward a Sustainable Future."},{"key":"e_1_3_3_1_39_2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO56248.2022.00070"},{"key":"e_1_3_3_1_40_2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO61859.2024.00041"},{"key":"e_1_3_3_1_41_2","doi-asserted-by":"crossref","unstructured":"Kevin Weston Farabi Mahmud Vahid Janfaza and Abdullah Muzahid. 2023. SmartIndex: Learning to Index Caches to Improve Performance. IEEE Computer Architecture Letters 22 (2023).","DOI":"10.1109\/LCA.2023.3264478"},{"key":"e_1_3_3_1_42_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2006.12"}],"event":{"name":"ICS '25: 2025 International Conference on Supercomputing","location":"Salt Lake City USA","acronym":"ICS '25","sponsor":["SIGARCH ACM Special Interest Group on Computer Architecture"]},"container-title":["Proceedings of the 39th ACM International Conference on Supercomputing"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3721145.3729513","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,22]],"date-time":"2025-08-22T13:00:27Z","timestamp":1755867627000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3721145.3729513"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,6,8]]},"references-count":41,"alternative-id":["10.1145\/3721145.3729513","10.1145\/3721145"],"URL":"https:\/\/doi.org\/10.1145\/3721145.3729513","relation":{},"subject":[],"published":{"date-parts":[[2025,6,8]]},"assertion":[{"value":"2025-08-22","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}