{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,21]],"date-time":"2025-11-21T11:32:35Z","timestamp":1763724755097,"version":"3.41.0"},"reference-count":157,"publisher":"Association for Computing Machinery (ACM)","issue":"2","license":[{"start":{"date-parts":[[2025,5,31]],"date-time":"2025-05-31T00:00:00Z","timestamp":1748649600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Reconfigurable Technol. Syst."],"published-print":{"date-parts":[[2025,6,30]]},"abstract":"<jats:p>\n            Cryptographic algorithms can be exploited by power side-channel attacks. Thus, it is imperative to perform a thorough pre-silicon security evaluation to minimize these potential threats. Conventional methods using FPGAs and CAD tools for pre-silicon power side-channel evaluation of CPUs can take a long time to complete. In this work, we propose CTScan, a novel platform that uses Coarse-Grained Reconfigurable Arrays (CGRAs) to speedup this evaluation. CTScan first maps the CPU microarchitecture onto the underlying CGRA hardware to mimic the execution patterns. Next, using the CPU instruction trace profiles obtained from a high-level simulator, we translate and then run these traces on the CGRA which allows for the emulated CPU power traces to be obtained for analysis. Our CGRA-based CTScan platform shows an end-to-end speedup improvement of up to 67\n            <jats:inline-formula content-type=\"math\/tex\">\n              <jats:tex-math notation=\"LaTeX\" version=\"MathJax\">\\(\\times\\)<\/jats:tex-math>\n            <\/jats:inline-formula>\n            speedup over state-of-the-art FPGAs for CPA attack, with comparable correlation to hypothesis. To the best of our knowledge, this is the first proposal that uses CGRAs as a platform for pre-silicon CPU security evaluation. CTScan has been validated against real silicon measurements on the Sakura-X FPGA board and a commercial RISC-V processor (SiFive FE310). Additionally, we present case studies to evaluate the applicability of CTScan when running two commonly used power side-channels.\n          <\/jats:p>","DOI":"10.1145\/3721294","type":"journal-article","created":{"date-parts":[[2025,3,3]],"date-time":"2025-03-03T14:10:37Z","timestamp":1741011037000},"page":"1-36","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["CTScan: A CGRA-based Platform for the Emulation of Power Side-Channel Attacks on Edge CPUs"],"prefix":"10.1145","volume":"18","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-5251-288X","authenticated-orcid":false,"given":"Yaswanth","family":"Tavva","sequence":"first","affiliation":[{"name":"Computer Science, National University of Singapore, Singapore, Singapore"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6015-1084","authenticated-orcid":false,"given":"Rohan","family":"Juneja","sequence":"additional","affiliation":[{"name":"Computer Science, National University of Singapore, Singapore, Singapore"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8742-134X","authenticated-orcid":false,"given":"Trevor E.","family":"Carlson","sequence":"additional","affiliation":[{"name":"Computer Science, National University of Singapore, Singapore, Singapore"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9010-6519","authenticated-orcid":false,"given":"Li-Shiuan","family":"Peh","sequence":"additional","affiliation":[{"name":"Computer Science, National University of Singapore, Singapore, Singapore"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2025,5,31]]},"reference":[{"key":"e_1_3_3_2_2","first-page":"1320","volume-title":"International Midwest Symposium on Circuits and Systems (MWSCAS)","author":"Adegbite Oluwadara","year":"2017","unstructured":"Oluwadara Adegbite and Syed Rafay Hasan. 2017. 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