{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,16]],"date-time":"2026-01-16T00:18:00Z","timestamp":1768522680147,"version":"3.49.0"},"publisher-location":"New York, NY, USA","reference-count":29,"publisher":"ACM","license":[{"start":{"date-parts":[[2025,3,30]],"date-time":"2025-03-30T00:00:00Z","timestamp":1743292800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by-sa\/4.0\/"}],"funder":[{"name":"German Federal Ministry of Education and Research (BMBF)","award":["16ME0129"],"award-info":[{"award-number":["16ME0129"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2025,3,30]]},"DOI":"10.1145\/3721888.3722095","type":"proceedings-article","created":{"date-parts":[[2025,3,31]],"date-time":"2025-03-31T14:47:26Z","timestamp":1743432446000},"page":"31-36","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["Compiler-aware AI Hardware Design for Edge Devices"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-6642-3976","authenticated-orcid":false,"given":"Paul","family":"Palomero Bernardo","sequence":"first","affiliation":[{"name":"University of T\u00fcbingen, T\u00fcbingen, Germany"}]},{"ORCID":"https:\/\/orcid.org\/0009-0009-7896-6351","authenticated-orcid":false,"given":"Patrick","family":"Schmid","sequence":"additional","affiliation":[{"name":"University of T\u00fcbingen, T\u00fcbingen, Germany"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1715-567X","authenticated-orcid":false,"given":"Christoph","family":"Gerum","sequence":"additional","affiliation":[{"name":"University of T\u00fcbingen, T\u00fcbingen, Germany"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1615-507X","authenticated-orcid":false,"given":"Oliver","family":"Bringmann","sequence":"additional","affiliation":[{"name":"University of T\u00fcbingen, T\u00fcbingen, Germany"}]}],"member":"320","published-online":{"date-parts":[[2025,3,31]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/3508352.3549424"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2020.3012320"},{"key":"e_1_3_2_1_3_1","volume-title":"Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 1--5.","author":"Bernardo Paul Palomero","year":"2024","unstructured":"Paul Palomero Bernardo, Patrick Schmid, Oliver Bringmann, Mohammed Iftekhar, Babak Sadiye, Wolfgang Mueller, Andreas Koch, Eyck Jentzsch, Axel Sauer, Ingo Feldner, et al. 2024. A scalable risc-v hardware platform for intelligent sensor processing. In 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 1--5."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"crossref","first-page":"602","DOI":"10.1038\/s41597-022-01726-3","article-title":"Rhode Island gastroenterology video capsule endoscopy data set","volume":"9","author":"Charoen Amber","year":"2022","unstructured":"Amber Charoen, Averill Guo, Panisara Fangsaard, Supakorn Taweechainaruemitr, Nuwee Wiwatwattana, Theekapun Charoenpong, and Harlan G Rich. 2022. Rhode Island gastroenterology video capsule endoscopy data set. Scientific Data 9, 1 (2022), 602.","journal-title":"Scientific Data"},{"key":"e_1_3_2_1_5_1","volume-title":"13th USENIX Symposium on Operating Systems Design and Implementation (OSDI 18)","author":"Chen Tianqi","year":"2018","unstructured":"Tianqi Chen, Thierry Moreau, Ziheng Jiang, Lianmin Zheng, Eddie Yan, Haichen Shen, Meghan Cowan, Leyuan Wang, Yuwei Hu, Luis Ceze, et al. 2018. {TVM}: An automated {End-to-End} optimizing compiler for deep learning. In 13th USENIX Symposium on Operating Systems Design and Implementation (OSDI 18). 578--594."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001177"},{"key":"e_1_3_2_1_7_1","unstructured":"CIRCT. 2024. Circuit IR Compilers and Tool. https:\/\/github.com\/llvm\/circt"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/3358198"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","unstructured":"John Guttag. 2010. CHB-MIT Scalp EEG Database (version 1.0.0). 10.13026\/C2K01R","DOI":"10.13026\/C2K01R"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/3520127"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/3534933"},{"key":"e_1_3_2_1_12_1","volume-title":"Maestro: A data-centric approach to understand reuse, performance, and hardware cost of dnn mappings","author":"Kwon Hyoukjun","year":"2020","unstructured":"Hyoukjun Kwon, Prasanth Chatarasi, Vivek Sarkar, Tushar Krishna, Michael Pellauer, and Angshuman Parashar. 2020. Maestro: A data-centric approach to understand reuse, performance, and hardware cost of dnn mappings. IEEE micro 40, 3 (2020), 20--29."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/3296957.3173176"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/CGO51591.2021.9370308"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2020.3030548"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA52012.2021.00062"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/3623278.3624767"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2021.3059962"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2017.7870353"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2019.00042"},{"key":"e_1_3_2_1_21_1","volume-title":"Manuel Eggimann, Jorge Tom\u00e1s G\u00f3mez, Ziyun Li, Syed Shakib Sarwar, Zhao Wang, et al.","author":"Prasad Arpan Suravi","year":"2024","unstructured":"Arpan Suravi Prasad, Moritz Scherer, Francesco Conti, Davide Rossi, Alfio Di Mauro, Manuel Eggimann, Jorge Tom\u00e1s G\u00f3mez, Ziyun Li, Syed Shakib Sarwar, Zhao Wang, et al. 2024. Siracusa: A 16 nm Heterogenous RISC-V SoC for Extended Reality With At-MRAM Neural Engine. IEEE Journal of Solid-State Circuits (2024)."},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/2499370.2462176"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2024.3445810"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD45719.2019.8942127"},{"key":"e_1_3_2_1_25_1","volume-title":"International Workshop on Machine Learning in Medical Imaging. Springer, 174--183","author":"Werner Julia","year":"2023","unstructured":"Julia Werner, Christoph Gerum, Moritz Reiber, J\u00f6rg Nick, and Oliver Bringmann. 2023. Precise localization within the GI tract by combining classification of CNNs and time-series analysis of HMMs. In International Workshop on Machine Learning in Medical Imaging. Springer, 174--183."},{"key":"e_1_3_2_1_26_1","volume-title":"Energy-Efficient Seizure Detection Suitable for Low-Power Applications. In 2024 International Joint Conference on Neural Networks (IJCNN). IEEE, 1--8.","author":"Werner Julia","year":"2024","unstructured":"Julia Werner, Bhavya Kohli, Paul Palomero Bernardo, Christoph Gerum, and Oliver Bringmann. 2024. Energy-Efficient Seizure Detection Suitable for Low-Power Applications. In 2024 International Joint Conference on Neural Networks (IJCNN). IEEE, 1--8."},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/3373376.3378514"},{"key":"e_1_3_2_1_28_1","volume-title":"Compiler technologies in deep learning co-design: A survey. Intelligent Computing 2","author":"Zhang Hongbin","year":"2023","unstructured":"Hongbin Zhang, Mingjie Xing, Yanjun Wu, and Chen Zhao. 2023. Compiler technologies in deep learning co-design: A survey. Intelligent Computing 2 (2023)."},{"key":"e_1_3_2_1_29_1","volume-title":"AutoAI2C: An Automated Hardware Generator for DNN Acceleration On Both FPGA and ASIC","author":"Zhang Yongan","year":"2024","unstructured":"Yongan Zhang, Xiaofan Zhang, Pengfei Xu, Yang Zhao, Cong Hao, Deming Chen, and Yingyan Lin. 2024. AutoAI2C: An Automated Hardware Generator for DNN Acceleration On Both FPGA and ASIC. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2024)."}],"event":{"name":"EdgeSys '25: 8th International Workshop on Edge Systems, Analytics and Networking","location":"World Trade Center Rotterdam Netherlands","acronym":"EdgeSys '25","sponsor":["SIGOPS ACM Special Interest Group on Operating Systems"]},"container-title":["Proceedings of the 8th International Workshop on Edge Systems, Analytics and Networking"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3721888.3722095","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3721888.3722095","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T01:09:48Z","timestamp":1750295388000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3721888.3722095"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,3,30]]},"references-count":29,"alternative-id":["10.1145\/3721888.3722095","10.1145\/3721888"],"URL":"https:\/\/doi.org\/10.1145\/3721888.3722095","relation":{},"subject":[],"published":{"date-parts":[[2025,3,30]]},"assertion":[{"value":"2025-03-31","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}