{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,24]],"date-time":"2026-01-24T14:50:16Z","timestamp":1769266216672,"version":"3.49.0"},"reference-count":42,"publisher":"Association for Computing Machinery (ACM)","issue":"1","funder":[{"name":"Department of the Air Force","award":["FA8702-15-D-0001"],"award-info":[{"award-number":["FA8702-15-D-0001"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["J. Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2026,1,31]]},"abstract":"<jats:p>The Field Programmable Gate Array (FPGA) market has seen significant growth due to the low cost and reduced time to market when compared to ASIC circuits. However, FPGAs\u2019 reconfigurable nature introduces security vulnerabilities that can be exploited by adversaries to obtain sensitive information. Physical Unclonable Functions (PUFs) have shown to be valuable security primitives. By leveraging manufacturing variations in a device, one can generate unique signatures that can be used for authentication and generation of secret keys. However, PUF implementation can be costly, taking up FPGA resources and requiring long design times. In this article, we propose a method which takes advantage of the FPGA look-up table (LUT) architecture to embed the PUF into functional logic circuits, reducing the cost and design time. We provide detailed implementation guidelines and evaluate the PUF\u2019s signature quality and stability under different environmental variations using a set of test-bench circuits. Our results demonstrate the effectiveness of our method in securing FPGA designs while reducing implementation costs and design time.<\/jats:p>","DOI":"10.1145\/3725533","type":"journal-article","created":{"date-parts":[[2025,3,20]],"date-time":"2025-03-20T11:43:33Z","timestamp":1742471013000},"page":"1-18","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["SPLIT PUF: Efficient PUF Implementation Using Underutilized FPGA Resource"],"prefix":"10.1145","volume":"22","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-0852-7937","authenticated-orcid":false,"given":"Christopher","family":"Vega","sequence":"first","affiliation":[{"name":"MIT Lincoln Laboratory, Lexington, Massachusetts, USA\u00a0and Electrical and Computer Engineering, Herbert Wertheim College of Engineering, University of Florida, Gainesville, Florida, USA"}]}],"member":"320","published-online":{"date-parts":[[2025,12,5]]},"reference":[{"key":"e_1_3_2_2_2","unstructured":"Straits Research. 2022. FPGA market by configuration (low-end FPGA mid-range FPGA high-end FPGA) technology (SRAM Flash Antifuse) node size (16 nm 20\u201390 nm and 90 nm) vertical and region (North America Europe APAC RoW) \u2013 Global Forecast to 2027. Retrieved from https:\/\/www.marketsandmarkets.com\/Market-Reports\/fpga-market-194123367.html"},{"key":"e_1_3_2_3_2","first-page":"1","volume-title":"ACM Journal on Emerging Technologies in Computing Systems (JETC)","volume":"18","author":"Anandakumar N. Nalla","year":"2022","unstructured":"N. Nalla Anandakumar, Mohammad S. Hashmi, and Somitra Kumar Sanadhya. 2022. Design and analysis of FPGA based PUFs with enhanced performance for hardware-oriented security. ACM Journal on Emerging Technologies in Computing Systems (JETC) 18, 4, Article 72 (2022), 1\u201326."},{"key":"e_1_3_2_4_2","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2021.06.001"},{"key":"e_1_3_2_5_2","volume-title":"Hardware Security: A Hands-on Learning Approach","author":"Bhunia Swarup","year":"2018","unstructured":"Swarup Bhunia and Mark Tehranipoor. 2018. Hardware Security: A Hands-on Learning Approach. Morgan Kaufmann."},{"key":"e_1_3_2_6_2","volume-title":"Physical Unclonable Functions in Theory and Practice","author":"B\u00f6hm Christoph","year":"2012","unstructured":"Christoph B\u00f6hm and Maximilian Hofer. 2012. Physical Unclonable Functions in Theory and Practice. Springer Science & Business Media."},{"key":"e_1_3_2_7_2","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2011.5955011"},{"key":"e_1_3_2_8_2","unstructured":"Brendon Chetwynd Kevin Bush and Kyle Ingols. 2022. Common evaluation platform. MIT Lincoln Laboratory. Retrieved from https:\/\/github.com\/mit-ll\/CEP.git"},{"key":"e_1_3_2_9_2","first-page":"2740","volume-title":"IEEE Transactions on Computers","volume":"72","author":"Cruz Jonathan","year":"2023","unstructured":"Jonathan Cruz, Christopher Posada, Naren Vikram Raj Masna, Prabuddha Chakraborty, Pravin Gaikwad, and Swarup Bhunia. 2023. A framework for automated exploration of trojan attack space in FPGA netlists. IEEE Transactions on Computers 72, 10 (2023), 2740\u20132751."},{"key":"e_1_3_2_10_2","doi-asserted-by":"publisher","DOI":"10.3390\/cryptography5030023"},{"key":"e_1_3_2_11_2","doi-asserted-by":"crossref","first-page":"2325","DOI":"10.1109\/ISCAS.2011.5938068","volume-title":"2011 IEEE International Symposium of Circuits and Systems (ISCAS)","author":"Fruhashi Kota","year":"2011","unstructured":"Kota Fruhashi, Mitsuru Shiozaki, Akitaka Fukushima, Takahiko Murayama, and Takeshi Fujino. 2011. The arbiter-PUF with high uniqueness utilizing novel arbiter circuit with delay-time measurement. In 2011 IEEE International Symposium of Circuits and Systems (ISCAS). IEEE, 2325\u20132328."},{"key":"e_1_3_2_12_2","doi-asserted-by":"publisher","DOI":"10.1109\/ViTECoN.2019.8899550"},{"key":"e_1_3_2_13_2","doi-asserted-by":"publisher","DOI":"10.1145\/586110.586132"},{"key":"e_1_3_2_14_2","doi-asserted-by":"publisher","DOI":"10.1145\/3338508.3359570"},{"key":"e_1_3_2_15_2","doi-asserted-by":"publisher","DOI":"10.1145\/3053681"},{"key":"e_1_3_2_16_2","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-74735-2_5"},{"key":"e_1_3_2_17_2","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2013.79"},{"key":"e_1_3_2_18_2","doi-asserted-by":"crossref","first-page":"205","DOI":"10.1007\/978-3-319-16214-0_17","volume-title":"International Symposium on Applied Reconfigurable Computing","author":"Habib Bilal","year":"2015","unstructured":"Bilal Habib, Jens-Peter Kaps, and Kris Gaj. 2015. Efficient SR-latch PUF. In International Symposium on Applied Reconfigurable Computing. Springer, 205\u2013216."},{"key":"e_1_3_2_19_2","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2014.2320516"},{"key":"e_1_3_2_20_2","first-page":"01","volume-title":"Proceedings of the Conference on RFID Security","volume":"7","author":"Holcomb Daniel E.","year":"2007","unstructured":"Daniel E. Holcomb, Wayne P. Burleson, Kevin Fu. 2007. Initial SRAM state as a fingerprint and source of true random numbers for RFID tags. In Proceedings of the Conference on RFID Security, Vol. 7, 01."},{"key":"e_1_3_2_21_2","unstructured":"ID Intrinsic. 2013. Product webpage."},{"key":"e_1_3_2_22_2","volume-title":"SRAM PUF: The Secure Silicon Fingerprint","author":"ID Intrinsic","year":"2016","unstructured":"ID Intrinsic. 2016. SRAM PUF: The Secure Silicon Fingerprint. Eindhoven, Netherlands."},{"key":"e_1_3_2_23_2","doi-asserted-by":"publisher","DOI":"10.1109\/4.287"},{"key":"e_1_3_2_24_2","doi-asserted-by":"publisher","DOI":"10.1109\/ReConFig.2016.7857187"},{"key":"e_1_3_2_25_2","doi-asserted-by":"crossref","first-page":"67","DOI":"10.1109\/HST.2008.4559053","volume-title":"2008 IEEE International Workshop on Hardware-Oriented Security and Trust","author":"Kumar Sandeep S.","year":"2008","unstructured":"Sandeep S. Kumar, Jorge Guajardo, Roel Maes, Geert-Jan Schrijen, and Pim Tuyls. 2008. The butterfly PUF protecting IP on every FPGA. In 2008 IEEE International Workshop on Hardware-Oriented Security and Trust. IEEE, 67\u201370."},{"key":"e_1_3_2_26_2","doi-asserted-by":"crossref","first-page":"3","DOI":"10.1007\/978-3-642-14452-3_1","volume-title":"Towards Hardware-Intrinsic Security. Information Security and Cryptography","author":"Maes Roel","year":"2010","unstructured":"Roel Maes and Ingrid Verbauwhede. 2010. Physically unclonable functions: A study on the state of the art and future research directions. Towards Hardware-Intrinsic Security. Information Security and Cryptography. A. R. Sadeghi and D. Naccache (Eds.), Springer, 3\u201337."},{"key":"e_1_3_2_27_2","first-page":"1","volume-title":"2010 IEEE International Workshop on Information Forensics and Security","author":"Majzoobi Mehrdad","year":"2010","unstructured":"Mehrdad Majzoobi, Farinaz Koushanfar, and Srinivas Devadas. 2010. FPGA PUF using programmable delay lines. In 2010 IEEE International Workshop on Information Forensics and Security. IEEE, 1\u20136."},{"key":"e_1_3_2_28_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2702607"},{"key":"e_1_3_2_29_2","doi-asserted-by":"publisher","DOI":"10.1063\/1.5079407"},{"key":"e_1_3_2_30_2","doi-asserted-by":"publisher","DOI":"10.1145\/3431920.3439285"},{"key":"e_1_3_2_31_2","doi-asserted-by":"publisher","DOI":"10.1109\/4.50312"},{"key":"e_1_3_2_32_2","doi-asserted-by":"publisher","DOI":"10.1109\/TIE.2007.898279"},{"key":"e_1_3_2_33_2","volume-title":"On the Foundations of Physical Unclonable Functions","author":"R\u00fchrmair Ulrich","year":"2009","unstructured":"Ulrich R\u00fchrmair, Jan S\u00f6lter, and Frank Sehnke. 2009.\u00a0On the Foundations of Physical Unclonable Functions. Technical Report 2009\/277. Cryptology ePrint Archive."},{"key":"e_1_3_2_34_2","doi-asserted-by":"publisher","DOI":"10.1016\/j.comnet.2020.107593"},{"key":"e_1_3_2_35_2","doi-asserted-by":"publisher","DOI":"10.1145\/1278480.1278484"},{"key":"e_1_3_2_36_2","unstructured":"Christopher Vega Patanjali SLPSK Shubhra Deb Paul and Swarup Bhunia. 2023. MeLPUF: Memory in logic PUF. In 2023 IEEE Physical Assurance and Inspection of Electronics (PAINE). IEEE."},{"key":"e_1_3_2_37_2","unstructured":"Xilinx Inc. 2022. 7 Series FPGAs Configurable Logic Block. Xilinx Inc. Retrieved from https:\/\/docs.xilinx.com\/v\/u\/en-US\/ug474_7Series_CLB"},{"key":"e_1_3_2_38_2","unstructured":"Xilinx Inc. 2022. UltraScale Architecture Libraries Guide. Xilinx Inc. Retrieved from https:\/\/docs.xilinx.com\/r\/en-US\/ug974-vivado-ultrascale-libraries\/LUT6_2"},{"key":"e_1_3_2_39_2","volume-title":"IEICE Electronics Express","author":"Xu Xiumin","year":"2017","unstructured":"Xiumin Xu, Huaguo Liang, Zhengfeng Huang, Cuiyun Jiang, Yiming Ouyang, Xiangsheng Fang, Tianming Ni, and Maoxiang Yi. 2017. A highly reliable butterfly PUF in SRAM-based FPGAs. IEICE Electronics Express 14 (2017), 20170551."},{"key":"e_1_3_2_40_2","doi-asserted-by":"publisher","DOI":"10.1007\/s13389-012-0044-0"},{"key":"e_1_3_2_41_2","first-page":"83","volume-title":"2021 IEEE 4th International Conference on Electronics Technology (ICET)","author":"Yao Liang","year":"2021","unstructured":"Liang Yao, Huaguo Liang, Zhengfeng Huang, Cuiyun Jiang, Maoxiang Yi, and Yingchun Lu. 2021. A lightweight configurable XOR RO-PUF design based on Xilinx FPGA. In 2021 IEEE 4th International Conference on Electronics Technology (ICET). IEEE, 83\u201388."},{"key":"e_1_3_2_42_2","doi-asserted-by":"publisher","DOI":"10.1145\/1289816.1289831"},{"key":"e_1_3_2_43_2","doi-asserted-by":"crossref","first-page":"107","DOI":"10.1109\/CADGraphics.2013.22","volume-title":"2013 International Conference on Computer-Aided Design and Computer Graphics","author":"Zhang Jiliang","year":"2013","unstructured":"Jiliang Zhang, Qiang Wu, Yongqiang Lyu, Qiang Zhou, Yici Cai, Yaping Lin, and Gang Qu. 2013. Design and implementation of a delay-based PUF for FPGA IP protection. In 2013 International Conference on Computer-Aided Design and Computer Graphics. IEEE, 107\u2013114."}],"container-title":["ACM Journal on Emerging Technologies in Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3725533","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,12,5]],"date-time":"2025-12-05T14:33:33Z","timestamp":1764945213000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3725533"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,12,5]]},"references-count":42,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2026,1,31]]}},"alternative-id":["10.1145\/3725533"],"URL":"https:\/\/doi.org\/10.1145\/3725533","relation":{},"ISSN":["1550-4832","1550-4840"],"issn-type":[{"value":"1550-4832","type":"print"},{"value":"1550-4840","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,12,5]]},"assertion":[{"value":"2024-02-29","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2025-03-16","order":2,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2025-12-05","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}