{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,10]],"date-time":"2025-10-10T01:23:32Z","timestamp":1760059412184,"version":"build-2065373602"},"publisher-location":"New York, NY, USA","reference-count":26,"publisher":"ACM","content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2025,10,12]]},"DOI":"10.1145\/3725783.3764400","type":"proceedings-article","created":{"date-parts":[[2025,10,9]],"date-time":"2025-10-09T17:50:12Z","timestamp":1760032212000},"page":"124-130","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["SHOC: A Simplified Programming Model for Hardware Offloading on DPUs"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0009-0005-1944-9363","authenticated-orcid":false,"given":"Florian","family":"Knauf","sequence":"first","affiliation":[{"name":"Leibniz University Hannover, Hannover, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3791-7114","authenticated-orcid":false,"given":"Jan S.","family":"Rellermeyer","sequence":"additional","affiliation":[{"name":"Leibniz University Hannover, Hannover, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2025,10,11]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2021.3114899"},{"key":"e_1_3_2_1_2_1","first-page":"6","volume-title":"2022 International Conference on Computer Communications and Networks (ICCCN)","author":"Barsellotti Luca","unstructured":"Luca Barsellotti, Faris Alhamed, Juan Jose Vegas Olmos, Francesco Paolucci, Piero Castoldi, and Filippo Cugini. Introducing data processing units (dpu) at the edge. In 2022 International Conference on Computer Communications and Networks (ICCCN), pages 1\u20136. IEEE, 2022."},{"key":"e_1_3_2_1_3_1","volume-title":"A survey of asynchronous programming using coroutines in the internet of things and embedded systems. ACM Transactions on Embedded Computing Systems (TECS), 18(3):1\u201321","author":"Belson Bruce","year":"2019","unstructured":"Bruce Belson, Jason Holdsworth, Wei Xiang, and Bronson Philippa. A survey of asynchronous programming using coroutines in the internet of things and embedded systems. ACM Transactions on Embedded Computing Systems (TECS), 18(3):1\u201321, 2019."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/2656877.2656890"},{"key":"e_1_3_2_1_5_1","first-page":"20","volume-title":"2021 IEEE Hot Chips 33 Symposium (HCS)","author":"Burstein Idan","unstructured":"Idan Burstein. Nvidia data center processing unit (dpu) architecture. In 2021 IEEE Hot Chips 33 Symposium (HCS), pages 1\u201320. IEEE, 2021."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICDCS47774.2020.00029"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/366663.366704"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/3184120"},{"key":"e_1_3_2_1_9_1","volume-title":"Coroutines, Ranges, and more","author":"Fertig Andreas","year":"2021","unstructured":"Andreas Fertig. Programming with C++ 20: Concepts, Coroutines, Ranges, and more. Fertig Publications, 2021."},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/3579370.3594769"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.14778\/3430915.3430932"},{"key":"e_1_3_2_1_12_1","volume-title":"Dpdpu: Data processing with dpus. arXiv preprint arXiv:2407.13658","author":"Hu Jiasheng","year":"2024","unstructured":"Jiasheng Hu, Philip A Bernstein, Jialin Li, and Qizhen Zhang. Dpdpu: Data processing with dpus. arXiv preprint arXiv:2407.13658, 2024."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.14778\/3632093.3632117"},{"key":"e_1_3_2_1_14_1","volume-title":"Paola Grosso, Animesh Trivedi, Jan Rellermeyer, Lin Wang, Alexandru Uta, and Francesco Regazzoni. Future computer systems and networking research in the netherlands: A manifesto","author":"Iosup Alexandru","year":"2022","unstructured":"Alexandru Iosup, Fernando Kuipers, Ana Lucia Varbanescu, Paola Grosso, Animesh Trivedi, Jan Rellermeyer, Lin Wang, Alexandru Uta, and Francesco Regazzoni. Future computer systems and networking research in the netherlands: A manifesto, 2022."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/3019612.3019783"},{"key":"e_1_3_2_1_16_1","volume-title":"Hot Chips: A Symposium on High Performance Chips","author":"Liguori Anthony","year":"2018","unstructured":"Anthony Liguori. The nitro project-next generation aws infrastructure. In Hot Chips: A Symposium on High Performance Chips, 2018."},{"key":"e_1_3_2_1_17_1","first-page":"378","volume-title":"2019 USENIX Annual Technical Conference (USENIX ATC 19)","author":"Liu Ming","year":"2019","unstructured":"Ming Liu, Simon Peter, Arvind Krishnamurthy, and Phitchaya Mangpo Phothilimthana. E3:{Energy-Efficient} microservices on {SmartNIC-Accelerated} servers. In 2019 USENIX Annual Technical Conference (USENIX ATC 19), pages 363\u2013378, 2019."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-10256-6"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/1462166.1462167"},{"key":"e_1_3_2_1_20_1","volume-title":"DOCA Core - NVIDIA Docs. https:\/\/docs.nvidia.com\/doca\/sdk\/doca+core\/index.html","author":"NVIDIA.","year":"2024","unstructured":"NVIDIA. DOCA Core - NVIDIA Docs. https:\/\/docs.nvidia.com\/doca\/sdk\/doca+core\/index.html, 2024. [Accessed 22. Nov. 2024]."},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/3584954.3584997"},{"key":"e_1_3_2_1_22_1","first-page":"679","volume-title":"13th USENIX Symposium on Operating Systems Design and Implementation (OSDI 18)","author":"Phothilimthana Phitchaya Mangpo","year":"2018","unstructured":"Phitchaya Mangpo Phothilimthana, Ming Liu, Antoine Kaufmann, Simon Peter, Rastislav Bodik, and Thomas Anderson. Floem: A programming system for {NIC-Accelerated} network applications. In 13th USENIX Symposium on Operating Systems Design and Implementation (OSDI 18), pages 663\u2013679, 2018."},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/3477132.3483555"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2020.3016891"},{"key":"e_1_3_2_1_25_1","volume-title":"Enancing infrastructure efficiency with azure boost dpu. https:\/\/techcommunity.microsoft.com\/blog\/AzureInfrastructureBlog\/enhancing-infrastructure-efficiency-with-azure-boost-dpu\/4298901","author":"Sindhu Pradeep","year":"2024","unstructured":"Pradeep Sindhu. Enancing infrastructure efficiency with azure boost dpu. https:\/\/techcommunity.microsoft.com\/blog\/AzureInfrastructureBlog\/enhancing-infrastructure-efficiency-with-azure-boost-dpu\/4298901, 2024. [Accessed 12. Jan. 2025]."},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/3624062.3624165"}],"event":{"name":"APSys '25: 16th ACM SIGOPS Asia-Pacific Workshop on Systems","location":"Lotte Hotel World, Emerald Hall Seoul Republic of Korea","acronym":"APSys '25","sponsor":["SIGOPS ACM Special Interest Group on Operating Systems"]},"container-title":["Proceedings of the 16th ACM SIGOPS Asia-Pacific Workshop on Systems"],"original-title":[],"deposited":{"date-parts":[[2025,10,9]],"date-time":"2025-10-09T17:50:39Z","timestamp":1760032239000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3725783.3764400"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,10,11]]},"references-count":26,"alternative-id":["10.1145\/3725783.3764400","10.1145\/3725783"],"URL":"https:\/\/doi.org\/10.1145\/3725783.3764400","relation":{},"subject":[],"published":{"date-parts":[[2025,10,11]]},"assertion":[{"value":"2025-10-11","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}