{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T05:06:38Z","timestamp":1750309598785,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":14,"publisher":"ACM","license":[{"start":{"date-parts":[[2025,3,1]],"date-time":"2025-03-01T00:00:00Z","timestamp":1740787200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"DOI":"10.13039\/100000015","name":"DOE U.S. Department of Energy","doi-asserted-by":"publisher","award":["DE-AC05-00OR22725"],"award-info":[{"award-number":["DE-AC05-00OR22725"]}],"id":[{"id":"10.13039\/100000015","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000015","name":"DOE U.S. Department of Energy","doi-asserted-by":"publisher","award":["DE-FOA-0002950"],"award-info":[{"award-number":["DE-FOA-0002950"]}],"id":[{"id":"10.13039\/100000015","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2025,3]]},"DOI":"10.1145\/3725798.3725805","type":"proceedings-article","created":{"date-parts":[[2025,5,13]],"date-time":"2025-05-13T10:40:50Z","timestamp":1747132850000},"page":"42-47","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Performance Impact and Trade-Offs for Tuning Key Architectural Parameters on CPU+GPU Systems"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-4004-4791","authenticated-orcid":false,"given":"Kazi","family":"Asifuzzaman","sequence":"first","affiliation":[{"name":"Oak Ridge National Laboratory, Oak Ridge, Tennessee, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8259-8891","authenticated-orcid":false,"given":"Narasinga Rao","family":"Miniskar","sequence":"additional","affiliation":[{"name":"Oak Ridge National Laboratory, Oak Ridge, Tennessee, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2590-5178","authenticated-orcid":false,"given":"William","family":"Godoy","sequence":"additional","affiliation":[{"name":"Oak Ridge National Laboratory, Oak Ridge, Tennessee, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5380-6951","authenticated-orcid":false,"given":"Oscar","family":"Hernandez","sequence":"additional","affiliation":[{"name":"Oak Ridge National Laboratory, Oak Ridge, Tennessee, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2449-6720","authenticated-orcid":false,"given":"Jeffrey S.","family":"Vetter","sequence":"additional","affiliation":[{"name":"Oak Ridge National Laboratory, Oak Ridge, Tennessee, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2025,5,13]]},"reference":[{"key":"e_1_3_3_1_2_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISOCC47750.2019.9027715"},{"key":"e_1_3_3_1_3_2","doi-asserted-by":"publisher","DOI":"10.1109\/E2SC.2016.012"},{"key":"e_1_3_3_1_4_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2009.4919648"},{"key":"e_1_3_3_1_5_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS51385.2021.00035"},{"key":"e_1_3_3_1_6_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2018.00058"},{"key":"e_1_3_3_1_7_2","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2017.8167757"},{"key":"e_1_3_3_1_8_2","unstructured":"JEDEC. 2020. High Bandwidth Memory DRAM (HBM1 HBM2)."},{"key":"e_1_3_3_1_9_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA45697.2020.00047"},{"key":"e_1_3_3_1_10_2","doi-asserted-by":"publisher","DOI":"10.1145\/3582016.3582044"},{"key":"e_1_3_3_1_11_2","unstructured":"Jan Meribold. 2017. Survey of CPU Caches. https:\/\/meribold.org\/2017\/10\/20\/survey-of-cpu-caches\/ Accessed: 2024-12-13."},{"key":"e_1_3_3_1_12_2","doi-asserted-by":"publisher","unstructured":"Jason Power Joel Hestness Marc\u00a0S. Orr Mark\u00a0D. Hill and David\u00a0A. Wood. 2015. gem5-gpu: A Heterogeneous CPU-GPU Simulator. IEEE Computer Architecture Letters 14 1 (2015) 34\u201336. 10.1109\/LCA.2014.2299539","DOI":"10.1109\/LCA.2014.2299539"},{"key":"e_1_3_3_1_13_2","doi-asserted-by":"publisher","DOI":"10.1145\/2370816.2370865"},{"key":"e_1_3_3_1_14_2","unstructured":"Vishnu Ramadas et. al.2023. Closing the Gap: Improving the Accuracy of gem5\u2019s GPU Models. NSF Public access (2023). https:\/\/par.nsf.gov\/biblio\/10468163"},{"key":"e_1_3_3_1_15_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2010.5452013"}],"event":{"name":"GPGPU 2025: 17th Workshop on General Purpose Processing Using GPU","acronym":"GPGPU 2025","location":"Las Vegas NV USA"},"container-title":["Proceedings of the 17th Workshop on General Purpose Processing Using GPU"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3725798.3725805","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3725798.3725805","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3725798.3725805","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T01:57:04Z","timestamp":1750298224000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3725798.3725805"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,3]]},"references-count":14,"alternative-id":["10.1145\/3725798.3725805","10.1145\/3725798"],"URL":"https:\/\/doi.org\/10.1145\/3725798.3725805","relation":{},"subject":[],"published":{"date-parts":[[2025,3]]},"assertion":[{"value":"2025-05-13","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}