{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,9]],"date-time":"2026-06-09T08:44:25Z","timestamp":1780994665197,"version":"3.54.1"},"publisher-location":"New York, NY, USA","reference-count":57,"publisher":"ACM","funder":[{"name":"Provincial Natural Science Foundation of China","award":["LH2023F103"],"award-info":[{"award-number":["LH2023F103"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2025,10,18]]},"DOI":"10.1145\/3725843.3756019","type":"proceedings-article","created":{"date-parts":[[2025,10,17]],"date-time":"2025-10-17T17:19:56Z","timestamp":1760721596000},"page":"1236-1249","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["FexMo: Enabling Fuse Execution Mode for Multi-task CGRAs"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-1189-7661","authenticated-orcid":false,"given":"Yufei","family":"Yang","sequence":"first","affiliation":[{"name":"Harbin Institute of Technology, Harbin, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1399-0352","authenticated-orcid":false,"given":"Chenhao","family":"Xie","sequence":"additional","affiliation":[{"name":"Beihang University, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7403-0163","authenticated-orcid":false,"given":"Chuliang","family":"Guo","sequence":"additional","affiliation":[{"name":"Harbin Institute of Technology, Harbin, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5834-9772","authenticated-orcid":false,"given":"Liansheng","family":"Liu","sequence":"additional","affiliation":[{"name":"Harbin Institute of Technology, Harbin, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7424-1008","authenticated-orcid":false,"given":"Xiyuan","family":"Peng","sequence":"additional","affiliation":[{"name":"Harbin Institute of Technology, Harbin, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9967-5427","authenticated-orcid":false,"given":"Datong","family":"Liu","sequence":"additional","affiliation":[{"name":"Harbin Institute of Technology, Harbin, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3315-5581","authenticated-orcid":false,"given":"Yu","family":"Peng","sequence":"additional","affiliation":[{"name":"Harbin Institute of Technology, Harbin, China"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2025,10,17]]},"reference":[{"key":"e_1_3_3_1_2_2","unstructured":"2025. AM625 data sheet product information and support | TI.com. https:\/\/www.ti.com\/product\/AM625"},{"key":"e_1_3_3_1_3_2","unstructured":"2025. gem5\/gem5. https:\/\/github.com\/gem5\/gem5"},{"key":"e_1_3_3_1_4_2","unstructured":"2025. Intel Atom\u00ae Processor C3338. https:\/\/www.intel.com\/content\/www\/us\/en\/products\/sku\/97928\/intel-atom-processor-c3338-4m-cache-up-to-2-20-ghz\/specifications.html"},{"key":"e_1_3_3_1_5_2","unstructured":"2025. The LLVM Compiler Infrastructure Project. https:\/\/llvm.org\/"},{"key":"e_1_3_3_1_6_2","unstructured":"2025. RK3562. https:\/\/www.rock-chips.com\/a\/en\/products\/RK35_Series\/2024\/0626\/1983.html"},{"key":"e_1_3_3_1_7_2","unstructured":"2025. RV1126. https:\/\/www.rock-chips.com\/a\/en\/products\/RV11_Series\/2020\/0427\/1076.html"},{"key":"e_1_3_3_1_8_2","unstructured":"2025. Tx510. http:\/\/www.tsingmicro.com\/tx510-product.html"},{"key":"e_1_3_3_1_9_2","doi-asserted-by":"publisher","DOI":"10.1109\/SASP.2011.5941087"},{"key":"e_1_3_3_1_10_2","doi-asserted-by":"publisher","DOI":"10.1109\/ICFPT56656.2022.9974339"},{"key":"e_1_3_3_1_11_2","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP52443.2021.00030"},{"key":"e_1_3_3_1_12_2","doi-asserted-by":"publisher","unstructured":"Peng Cao Bo Liu Jinjiang Yang Jun Yang Meng Zhang and Longxing Shi. 2017. Context Management Scheme Optimization of Coarse-Grained Reconfigurable Architecture for Multimedia Applications. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 8 (Aug. 2017) 2321\u20132331. 10.1109\/TVLSI.2017.2695493","DOI":"10.1109\/TVLSI.2017.2695493"},{"key":"e_1_3_3_1_13_2","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2017.8203842"},{"key":"e_1_3_3_1_14_2","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2017.7995277"},{"key":"e_1_3_3_1_15_2","doi-asserted-by":"publisher","unstructured":"Lawrence\u00a0T. Clark Vinay Vashishtha Lucian Shifren Aditya Gujja Saurabh Sinha Brian Cline Chandarasekaran Ramamurthy and Greg Yeric. 2016. ASAP7: A 7-nm finFET predictive process design kit. Microelectronics Journal 53 (2016) 105\u2013115. 10.1016\/j.mejo.2016.04.006","DOI":"10.1016\/j.mejo.2016.04.006"},{"key":"e_1_3_3_1_16_2","doi-asserted-by":"publisher","unstructured":"Kathleen Feng Taeyoung Kong Kalhan Koul Jackson Melchert Alex Carsello Qiaoyi Liu Gedeon Nyengele Maxwell Strange Keyi Zhang Ankita Nayak Jeff Setter James Thomas Kavya Sreedhar Po-Han Chen Nikhil Bhagdikar Zach\u00a0A. Myers Brandon D\u2019Agostino Pranil Joshi Stephen Richardson Christopher Torng Mark Horowitz and Priyanka Raina. 2024. Amber: A 16-nm System-on-Chip With a Coarse- Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra. IEEE Journal of Solid-State Circuits 59 3 (March 2024) 947\u2013959. 10.1109\/JSSC.2023.3313116Conference Name: IEEE Journal of Solid-State Circuits.","DOI":"10.1109\/JSSC.2023.3313116"},{"key":"e_1_3_3_1_17_2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO56248.2022.00046"},{"key":"e_1_3_3_1_18_2","doi-asserted-by":"publisher","DOI":"10.1145\/3061639.3062262"},{"key":"e_1_3_3_1_19_2","doi-asserted-by":"publisher","DOI":"10.5555\/3291168.3291177"},{"key":"e_1_3_3_1_20_2","doi-asserted-by":"publisher","unstructured":"Taeyoung Kong Kalhan Koul Priyanka Raina Mark Horowitz and Christopher Torng. 2023. Hardware Abstractions and Hardware Mechanisms to Support Multi-Task Execution on Coarse-Grained Reconfigurable Arrays. 10.48550\/arXiv.2301.00861arXiv:https:\/\/arXiv.org\/abs\/2301.00861 [cs].","DOI":"10.48550\/arXiv.2301.00861"},{"key":"e_1_3_3_1_21_2","doi-asserted-by":"publisher","DOI":"10.1145\/3579371.3589081"},{"key":"e_1_3_3_1_22_2","doi-asserted-by":"publisher","unstructured":"Zhaoying Li Dhananjaya Wijerathne Xianzhang Chen Anuj Pathania and Tulika Mitra. 2022. ChordMap: Automated Mapping of Streaming Applications Onto CGRA. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 41 2 (Feb. 2022) 306\u2013319. 10.1109\/TCAD.2021.3058313Conference Name: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.","DOI":"10.1109\/TCAD.2021.3058313"},{"key":"e_1_3_3_1_23_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA53966.2022.00040"},{"key":"e_1_3_3_1_24_2","doi-asserted-by":"publisher","unstructured":"Dajiang Liu Shouyi Yin Guojie Luo Jiaxing Shang Leibo Liu Shaojun Wei Yong Feng and Shangbo Zhou. 2019. Data-Flow Graph Mapping Optimization for CGRA With Deep Reinforcement Learning. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 38 12 (Dec. 2019) 2271\u20132283. 10.1109\/TCAD.2018.2878183Conference Name: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.","DOI":"10.1109\/TCAD.2018.2878183"},{"key":"e_1_3_3_1_25_2","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750414"},{"key":"e_1_3_3_1_26_2","doi-asserted-by":"publisher","unstructured":"Leibo Liu Zhaoshi Li Chen Yang Chenchen Deng Shouyi Yin and Shaojun Wei. 2018. HReA: An Energy-Efficient Embedded Dynamically Reconfigurable Fabric for 13-Dwarfs Processing. IEEE Transactions on Circuits and Systems II: Express Briefs 65 3 (March 2018) 381\u2013385. 10.1109\/TCSII.2017.2728814Conference Name: IEEE Transactions on Circuits and Systems II: Express Briefs.","DOI":"10.1109\/TCSII.2017.2728814"},{"key":"e_1_3_3_1_27_2","doi-asserted-by":"publisher","unstructured":"Leibo Liu Chen Yang Shouyi Yin and Shaojun Wei. 2018. CDPM: Context-Directed Pattern Matching Prefetching to Improve Coarse-Grained Reconfigurable Array Performance. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37 6 (June 2018) 1171\u20131184. 10.1109\/TCAD.2017.2748026","DOI":"10.1109\/TCAD.2017.2748026"},{"key":"e_1_3_3_1_28_2","doi-asserted-by":"publisher","unstructured":"Leibo Liu Jianfeng Zhu Zhaoshi Li Yanan Lu Yangdong Deng Jie Han Shouyi Yin and Shaojun Wei. 2019. A Survey of Coarse-Grained Reconfigurable Architecture and Design: Taxonomy Challenges and Applications. Comput. Surveys 52 6 (Oct. 2019) 118:1\u2013118:39. 10.1145\/3357375","DOI":"10.1145\/3357375"},{"key":"e_1_3_3_1_29_2","doi-asserted-by":"publisher","DOI":"10.1145\/3470496.3527426"},{"key":"e_1_3_3_1_30_2","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2002.1188678"},{"key":"e_1_3_3_1_31_2","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cdt:20030833"},{"key":"e_1_3_3_1_32_2","doi-asserted-by":"publisher","DOI":"10.1109\/HCS61935.2024.10665106"},{"key":"e_1_3_3_1_33_2","doi-asserted-by":"publisher","unstructured":"Artur Podobas Kentaro Sano and Satoshi Matsuoka. 2020. A Survey on Coarse-Grained Reconfigurable Architectures From a Performance Perspective. IEEE Access 8 (2020) 146719\u2013146743. 10.1109\/ACCESS.2020.3012084Conference Name: IEEE Access.","DOI":"10.1109\/ACCESS.2020.3012084"},{"key":"e_1_3_3_1_34_2","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080256"},{"key":"e_1_3_3_1_35_2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1994.717412"},{"key":"e_1_3_3_1_36_2","unstructured":"Matthias Reisinger. 2025. MatthiasJReisinger\/PolyBenchC-4.2.1. https:\/\/github.com\/MatthiasJReisinger\/PolyBenchC-4.2.1 original-date: 2016-06-10T11:45:57Z."},{"key":"e_1_3_3_1_37_2","doi-asserted-by":"publisher","unstructured":"Karthikeyan Sankaralingam Ramadass Nagarajan Haiming Liu Changkyu Kim Jaehyuk Huh Nitya Ranganathan Doug Burger Stephen\u00a0W. Keckler Robert\u00a0G. McDonald and Charles\u00a0R. Moore. 2004. TRIPS: A polymorphous architecture for exploiting ILP TLP and DLP. ACM Transactions on Architecture and Code Optimization 1 1 (March 2004) 62\u201393. 10.1145\/980152.980156","DOI":"10.1145\/980152.980156"},{"key":"e_1_3_3_1_38_2","doi-asserted-by":"publisher","DOI":"10.1145\/3613424.3614283"},{"key":"e_1_3_3_1_39_2","doi-asserted-by":"publisher","unstructured":"Aviral Shrivastava Reiley Jeyapaul and Aviral Shrivastava. 2015. A Software Scheme for Multithreading on CGRAs. ACM Transactions on Embedded Computing Systems 14 1 (Jan. 2015) 19:1\u201319:26. 10.1145\/2638558","DOI":"10.1145\/2638558"},{"key":"e_1_3_3_1_40_2","unstructured":"Cheng Tan. 2025. tancheng\/CGRA-Mapper. https:\/\/github.com\/tancheng\/CGRA-Mapper original-date: 2019-08-14T15:43:14Z."},{"key":"e_1_3_3_1_41_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA53966.2022.00030"},{"key":"e_1_3_3_1_42_2","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD53106.2021.00018"},{"key":"e_1_3_3_1_43_2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO61859.2024.00099"},{"key":"e_1_3_3_1_44_2","doi-asserted-by":"publisher","unstructured":"Cheng Tan Chenhao Xie Tong Geng Andres Marquez Antonino Tumeo Kevin Barker and Ang Li. 2021. ARENA: Asynchronous Reconfigurable Accelerator Ring to Enable Data-Centric Parallel Computing. IEEE Transactions on Parallel and Distributed Systems 32 12 (Dec. 2021) 2880\u20132892. 10.1109\/TPDS.2021.3081074Conference Name: IEEE Transactions on Parallel and Distributed Systems.","DOI":"10.1109\/TPDS.2021.3081074"},{"key":"e_1_3_3_1_45_2","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD50377.2020.00070"},{"key":"e_1_3_3_1_46_2","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD50377.2020.00070"},{"key":"e_1_3_3_1_47_2","doi-asserted-by":"publisher","DOI":"10.23919\/DATE51398.2021.9473955"},{"key":"e_1_3_3_1_48_2","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2018.00028"},{"key":"e_1_3_3_1_49_2","doi-asserted-by":"publisher","unstructured":"Shaojun Wei Xinhan Lin Fengbin Tu Yang Wang Leibo Liu and Shouyi Yin. 2023. Reconfigurability Why It Matters in AI Tasks Processing: A Survey of Reconfigurable AI Chips. IEEE Transactions on Circuits and Systems I: Regular Papers 70 3 (March 2023) 1228\u20131241. 10.1109\/TCSI.2022.3228860Conference Name: IEEE Transactions on Circuits and Systems I: Regular Papers.","DOI":"10.1109\/TCSI.2022.3228860"},{"key":"e_1_3_3_1_50_2","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-71431-63"},{"key":"e_1_3_3_1_51_2","doi-asserted-by":"publisher","DOI":"10.1109\/DAC56929.2023.10247776"},{"key":"e_1_3_3_1_52_2","doi-asserted-by":"publisher","unstructured":"Chen Yang Leibo Liu Kai Luo Shouyi Yin and Shaojun Wei. 2017. CIACP: A Correlation- and Iteration- Aware Cache Partitioning Mechanism to Improve Performance of Multiple Coarse-Grained Reconfigurable Arrays. IEEE Transactions on Parallel and Distributed Systems 28 1 (Jan. 2017) 29\u201343. 10.1109\/TPDS.2016.2554278","DOI":"10.1109\/TPDS.2016.2554278"},{"key":"e_1_3_3_1_53_2","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2898001"},{"key":"e_1_3_3_1_54_2","doi-asserted-by":"publisher","unstructured":"Yufei Yang Chenhao Xie Rui Wang Liansheng Liu Xiyuan Peng and Yu Peng. 2025. MultiSky: Dynamic Resource Allocation Framework for High-Throughput CGRA Multi-Task Execution. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2025) 1\u20131. 10.1109\/TCAD.2025.3597525","DOI":"10.1109\/TCAD.2025.3597525"},{"key":"e_1_3_3_1_55_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2017.8050274"},{"key":"e_1_3_3_1_56_2","doi-asserted-by":"publisher","DOI":"10.1145\/3373376.3378491"},{"key":"e_1_3_3_1_57_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA52012.2021.00085"},{"key":"e_1_3_3_1_58_2","doi-asserted-by":"publisher","DOI":"10.1109\/ICFPT59805.2023.00054"}],"event":{"name":"MICRO 2025: 58th IEEE\/ACM International Symposium on Microarchitecture","location":"Seoul Korea","acronym":"MICRO 2025","sponsor":["SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing"]},"container-title":["Proceedings of the 58th IEEE\/ACM International Symposium on Microarchitecture"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3725843.3756019","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,1,26]],"date-time":"2026-01-26T21:44:33Z","timestamp":1769463873000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3725843.3756019"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,10,17]]},"references-count":57,"alternative-id":["10.1145\/3725843.3756019","10.1145\/3725843"],"URL":"https:\/\/doi.org\/10.1145\/3725843.3756019","relation":{},"subject":[],"published":{"date-parts":[[2025,10,17]]},"assertion":[{"value":"2025-10-17","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}