{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,23]],"date-time":"2026-04-23T08:03:30Z","timestamp":1776931410471,"version":"3.51.2"},"publisher-location":"New York, NY, USA","reference-count":34,"publisher":"ACM","funder":[{"DOI":"10.13039\/501100000266","name":"Engineering and Physical Sciences Research Council","doi-asserted-by":"publisher","award":["EP\/W00576X\/1"],"award-info":[{"award-number":["EP\/W00576X\/1"]}],"id":[{"id":"10.13039\/501100000266","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Arm Ltd","award":["G109930"],"award-info":[{"award-number":["G109930"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2025,10,18]]},"DOI":"10.1145\/3725843.3756051","type":"proceedings-article","created":{"date-parts":[[2025,10,17]],"date-time":"2025-10-17T17:21:19Z","timestamp":1760721679000},"page":"490-503","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["LoopFrog: In-Core Hint-Based Loop Parallelization"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-5146-4361","authenticated-orcid":false,"given":"Marton","family":"Erdos","sequence":"first","affiliation":[{"name":"University of Cambridge, Cambridge, United Kingdom"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0076-1059","authenticated-orcid":false,"given":"Utpal","family":"Bora","sequence":"additional","affiliation":[{"name":"University of Cambridge, Cambridge, United Kingdom"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1264-5274","authenticated-orcid":false,"given":"Akshay","family":"Bhosale","sequence":"additional","affiliation":[{"name":"University of Cambridge, Cambridge, United Kingdom"}]},{"ORCID":"https:\/\/orcid.org\/0009-0000-6157-3185","authenticated-orcid":false,"given":"Bob","family":"Lytton","sequence":"additional","affiliation":[{"name":"Arm, Cambridge, United Kingdom"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4894-0603","authenticated-orcid":false,"given":"Ali M.","family":"Zaidi","sequence":"additional","affiliation":[{"name":"Arm, Cambridge, United Kingdom"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4091-5355","authenticated-orcid":false,"given":"Alexandra W.","family":"Chadwick","sequence":"additional","affiliation":[{"name":"University of Cambridge, Cambridge, United Kingdom"}]},{"ORCID":"https:\/\/orcid.org\/0009-0007-0169-3864","authenticated-orcid":false,"given":"Yuxin","family":"Guo","sequence":"additional","affiliation":[{"name":"University of Cambridge, Cambridge, United Kingdom"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3179-5873","authenticated-orcid":false,"given":"Giacomo","family":"Gabrielli","sequence":"additional","affiliation":[{"name":"Arm, Cambridge, United Kingdom"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4114-7661","authenticated-orcid":false,"given":"Timothy M.","family":"Jones","sequence":"additional","affiliation":[{"name":"University of Cambridge, Cambridge, United Kingdom"}]}],"member":"320","published-online":{"date-parts":[[2025,10,17]]},"reference":[{"key":"e_1_3_3_2_2_2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1998.742784"},{"key":"e_1_3_3_2_3_2","doi-asserted-by":"publisher","unstructured":"Nathan Binkert Bradford Beckmann Gabriel Black Steven\u00a0K. Reinhardt Ali Saidi Arkaprava Basu Joel Hestness Derek\u00a0R. Hower Tushar Krishna Somayeh Sardashti Rathijit Sen Korey Sewell Muhammad Shoaib Nilay Vaish Mark\u00a0D. Hill and David\u00a0A. Wood. 2011. The gem5 Simulator. ACM SIGARCH Computer Architecture News 39 2 (2011). 10.1145\/2024716.2024718","DOI":"10.1145\/2024716.2024718"},{"key":"e_1_3_3_2_4_2","doi-asserted-by":"publisher","DOI":"10.1145\/1278480.1278667"},{"key":"e_1_3_3_2_5_2","doi-asserted-by":"publisher","unstructured":"J. Burns and J.-L. Gaudiot. 2002. SMT Layout Overhead and Scalability. IEEE Transactions on Parallel and Distributed Systems 13 2 (2002). 10.1109\/71.983942","DOI":"10.1109\/71.983942"},{"key":"e_1_3_3_2_6_2","doi-asserted-by":"publisher","unstructured":"Simone Campanoni Timothy\u00a0M. Jones Glenn Holloway Gu-Yeon Wei and David Brooks. 2012. HELIX: Making the Extraction of Thread-Level Parallelism Mainstream. IEEE Micro 32 4 (2012). 10.1109\/MM.2012.50","DOI":"10.1109\/MM.2012.50"},{"key":"e_1_3_3_2_7_2","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000108"},{"key":"e_1_3_3_2_8_2","doi-asserted-by":"publisher","unstructured":"Alvaro Estebanez Diego\u00a0R. Llanos and Arturo Gonzalez-Escribano. 2016. A Survey on Thread-Level Speculation Techniques. Comput. Surveys 49 2 (2016). 10.1145\/2938369","DOI":"10.1145\/2938369"},{"key":"e_1_3_3_2_9_2","doi-asserted-by":"publisher","DOI":"10.1145\/3466752.3480045"},{"key":"e_1_3_3_2_10_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2016.7446103"},{"key":"e_1_3_3_2_11_2","unstructured":"Greg Hamerly Erez Perelman Jeremy Lau and Brad Calder. 2005. SimPoint 3.0: Faster and More Flexible Program Phase Analysis. Journal of Instruction Level Parallelism 7 4 (2005). http:\/\/www.jilp.org\/vol7\/v7paper14.pdf"},{"key":"e_1_3_3_2_12_2","doi-asserted-by":"publisher","DOI":"10.1145\/165123.165164"},{"key":"e_1_3_3_2_13_2","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830777"},{"key":"e_1_3_3_2_14_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00045"},{"key":"e_1_3_3_2_15_2","doi-asserted-by":"publisher","DOI":"10.1109\/CGO.2004.1281665"},{"key":"e_1_3_3_2_16_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2005.25"},{"key":"e_1_3_3_2_17_2","doi-asserted-by":"publisher","unstructured":"Carlos Madriles Carlos\u00a0Garc\u00eda Qui\u00f1ones F.\u00a0Jes\u00fas S\u00e1nchez Pedro Marcuello Antonio Gonz\u00e1lez Dean\u00a0M. Tullsen Hong Wang and John\u00a0Paul Shen. 2008. Mitosis: A Speculative Multithreaded Processor Based on Precomputation Slices. IEEE Transactions on Parallel Distributed Systems 19 7 (2008) 914\u2013925. 10.1109\/TPDS.2007.70797","DOI":"10.1109\/TPDS.2007.70797"},{"key":"e_1_3_3_2_18_2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1999.809461"},{"key":"e_1_3_3_2_19_2","unstructured":"Naveen Muralimanohar Rajeev Balasubramonian and Norman\u00a0P Jouppi. 2009. CACTI 6.0: A tool to model large caches. HP laboratories 27 (2009). https:\/\/www.hpl.hp.com\/techreports\/2009\/HPL-2009-85.pdf"},{"key":"e_1_3_3_2_20_2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO50266.2020.00056"},{"key":"e_1_3_3_2_21_2","doi-asserted-by":"publisher","unstructured":"M. Ohmacht A. Wang T. Gooding B. Nathanson I. Nair G. Janssen M. Schaal and B. Steinmacher-Burow. 2013. IBM Blue Gene\/Q memory subsystem with speculative execution and transactional memory. IBM Journal of Research and Development 57 1 (2013). 10.1147\/JRD.2012.2228092","DOI":"10.1147\/JRD.2012.2228092"},{"key":"e_1_3_3_2_22_2","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859624"},{"key":"e_1_3_3_2_23_2","doi-asserted-by":"publisher","unstructured":"Andrea Pellegrini Nigel Stephens Magnus Bruce Yasuo Ishii Joseph Pusdesris Abhishek Raja Chris Abernathy Jinson Koppanalil Tushar Ringe Ashok Tummala Jamshed Jalal Mark Werkheiser and Anitha Kona. 2020. The Arm Neoverse N1 Platform: Building Blocks for the Next-Gen Cloud-to-Edge Infrastructure SoC. IEEE Micro 40 2 (2020). 10.1109\/MM.2020.2972222","DOI":"10.1109\/MM.2020.2972222"},{"key":"e_1_3_3_2_24_2","doi-asserted-by":"publisher","DOI":"10.1145\/3018743.3018758"},{"key":"e_1_3_3_2_25_2","unstructured":"Andr\u00e9 Seznec. 2007. A 256 Kbits L-TAGE branch predictor. https:\/\/www.irisa.fr\/caps\/people\/seznec\/L-TAGE.pdf."},{"key":"e_1_3_3_2_26_2","doi-asserted-by":"publisher","unstructured":"Balaram Sinharoy Ronald\u00a0N. Kalla Joel\u00a0M. Tendler Richard\u00a0J. Eickemeyer and Jody\u00a0B. Joyner. 2005. POWER5 system microarchitecture. IBM Journal of Research and Development 49 4-5 (2005) 505\u2013522. 10.1147\/RD.494.0505","DOI":"10.1147\/RD.494.0505"},{"key":"e_1_3_3_2_27_2","doi-asserted-by":"publisher","unstructured":"Balaram Sinharoy James\u00a0Van Norstrand Richard\u00a0J. Eickemeyer Hung\u00a0Q. Le Jens Leenstra Dung\u00a0Q. Nguyen B. Konigsburg K. Ward M.\u00a0D. Brown Jos\u00e9\u00a0E. Moreira D. Levitan S. Tung David Hrusecky James\u00a0W. Bishop Michael Gschwind Maarten Boersma Michael Kroener Markus Kaltenbach Tejas Karkhanis and K.\u00a0M. Fernsler. 2015. IBM POWER8 processor core microarchitecture. IBM Journal of Research and Development 59 1 (2015). 10.1147\/JRD.2014.2376112","DOI":"10.1147\/JRD.2014.2376112"},{"key":"e_1_3_3_2_28_2","doi-asserted-by":"publisher","DOI":"10.1145\/223982.224451"},{"key":"e_1_3_3_2_29_2","doi-asserted-by":"publisher","unstructured":"J.\u00a0Gregory Steffan Christopher Colohan Antonia Zhai and Todd\u00a0C. Mowry. 2005. The STAMPede Approach to Thread-Level Speculation. ACM Transactions on Computer Systems 23 3 (2005). 10.1145\/1082469.1082471","DOI":"10.1145\/1082469.1082471"},{"key":"e_1_3_3_2_30_2","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080218"},{"key":"e_1_3_3_2_31_2","doi-asserted-by":"publisher","DOI":"10.1007\/978-0-387-09766-4170"},{"key":"e_1_3_3_2_32_2","doi-asserted-by":"publisher","DOI":"10.5555\/1299042.1299110"},{"key":"e_1_3_3_2_33_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2014.6844459"},{"key":"e_1_3_3_2_34_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA45697.2020.00024"},{"key":"e_1_3_3_2_35_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS51385.2021.00030"}],"event":{"name":"MICRO 2025: 58th IEEE\/ACM International Symposium on Microarchitecture","location":"Seoul Korea","acronym":"MICRO 2025","sponsor":["SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing"]},"container-title":["Proceedings of the 58th IEEE\/ACM International Symposium on Microarchitecture"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3725843.3756051","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,1,26]],"date-time":"2026-01-26T21:48:44Z","timestamp":1769464124000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3725843.3756051"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,10,17]]},"references-count":34,"alternative-id":["10.1145\/3725843.3756051","10.1145\/3725843"],"URL":"https:\/\/doi.org\/10.1145\/3725843.3756051","relation":{},"subject":[],"published":{"date-parts":[[2025,10,17]]},"assertion":[{"value":"2025-10-17","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}