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Existing netlist-based partitioning algorithms mostly targeting for cut size minimization do not handle performance well. In this article, we propose an Integer Linear Programming (ILP)-based algorithmic-level design partitioning algorithm for latency minimization. Our ILP formulation considers both partition resource constraints and inter-chip routing resource constraints. Multi-cycle communication is considered to address large inter-chip delay, together with local cache design for inter-chip data transmission bandwidth. For 2.5D FPGAs, our approach can improve the final clock frequency by 74.3% and circuit runtime by 60.2% when compared to Vivado. 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