{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,30]],"date-time":"2025-07-30T14:25:34Z","timestamp":1753885534505,"version":"3.41.2"},"reference-count":50,"publisher":"Association for Computing Machinery (ACM)","issue":"4","funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"crossref","award":["62202483"],"award-info":[{"award-number":["62202483"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"crossref"}]},{"DOI":"10.13039\/501100004735","name":"Hunan Provincial Natural Science Foundation of China","doi-asserted-by":"crossref","award":["2022JJ40563"],"award-info":[{"award-number":["2022JJ40563"]}],"id":[{"id":"10.13039\/501100004735","id-type":"DOI","asserted-by":"crossref"}]},{"name":"Open Project Program of Wuhan National Laboratory for Optoelectronics","award":["2021WNLOKF019"],"award-info":[{"award-number":["2021WNLOKF019"]}]},{"DOI":"10.13039\/501100007085","name":"NUDT","doi-asserted-by":"crossref","award":["22-ZZCX-046"],"award-info":[{"award-number":["22-ZZCX-046"]}],"id":[{"id":"10.13039\/501100007085","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2025,7,31]]},"abstract":"<jats:p>Memristor stateful logic is an effective way to achieve the real sense of in-memory computing in memristor-based crossbar array (MCBA). At present, the synthesis tools fall short in conducting a thorough exploration of the optimization potential pertaining to cascading stateful logic gates within MCBA, and the optimization objectives are relatively simple. In this article, a suit of stateful logic synthesis kit, named ILOSSS, improved from the previous LOSSS tool is achieved. Such kit includes two kinds of stateful logic synthesis processes for latency (corresponding to the High Time-Efficiency Synthesis Process (HTESP)) and energy (corresponding to the Low-Energy Synthesis Process (LESP)) optimization, respectively. Both of the synthesis processes are achieved by improving an existing synthesis process of MAGIC (SIMPLER-MAGIC) to support multiple stateful logic gates and inserting a post-processing stage with a well-developed automated optimization algorithm to reduce the number of the gates of the netlist with a corresponding purpose. Comparing to the standard SIMPLER-MAGIC tool, the HTESP achieves arithmetic mean improvements of over 23% in performance, and over 34% in effective lifetime under the EPFL benchmark suit which is also better than the results reported by the state-of-the-art MAGIC synthesis process (X-MAGIC). Meanwhile, the energy-delay product (EDP) of LESP has decreased by an average of over 10% and 42% compared to SIMPLER-MAGIC and HTESP, respectively.<\/jats:p>","DOI":"10.1145\/3731245","type":"journal-article","created":{"date-parts":[[2025,4,21]],"date-time":"2025-04-21T07:07:26Z","timestamp":1745219246000},"page":"1-23","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["ILOSSS - Improved Logic Synthesis based on Several Stateful Logic Gates"],"prefix":"10.1145","volume":"30","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-1224-7345","authenticated-orcid":false,"given":"Nuo","family":"Xu","sequence":"first","affiliation":[{"name":"College of Computer Science and Technology & Key Laboratory of Advanced Microprocessor Chips and Systems, National University of Defense Technology","place":["Changsha, China"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6651-0685","authenticated-orcid":false,"given":"Yihong","family":"Hu","sequence":"additional","affiliation":[{"name":"College of Computer Science and Technology & Key Laboratory of Advanced Microprocessor Chips and Systems, National University of Defense Technology","place":["Changsha, China"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1889-6912","authenticated-orcid":false,"given":"Chaochao","family":"Feng","sequence":"additional","affiliation":[{"name":"College of Computer Science and Technology & Key Laboratory of Advanced Microprocessor Chips and Systems, National University of Defense Technology","place":["Changsha, China"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8834-4953","authenticated-orcid":false,"given":"Wei","family":"Tong","sequence":"additional","affiliation":[{"name":"Wuhan National Laboratory for Optoelectronics, Huazhong University of Science and Technology","place":["Wuhan, China"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0001-7574-1618","authenticated-orcid":false,"given":"Kang","family":"Liu","sequence":"additional","affiliation":[{"name":"College of Computer Science and Technology & Key Laboratory of Advanced Microprocessor Chips and Systems, National University of Defense Technology","place":["Changsha, China"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3498-3685","authenticated-orcid":false,"given":"Liang","family":"Fang","sequence":"additional","affiliation":[{"name":"College of Computer Science and Technology, National University of Defense Technology","place":["Changsha, China"]}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2025,7,9]]},"reference":[{"key":"e_1_3_1_2_2","doi-asserted-by":"publisher","DOI":"10.1145\/216585.216588"},{"key":"e_1_3_1_3_2","doi-asserted-by":"publisher","DOI":"10.1147\/JRD.2019.2934048"},{"key":"e_1_3_1_4_2","doi-asserted-by":"publisher","DOI":"10.1038\/s41928-023-01053-4"},{"key":"e_1_3_1_5_2","doi-asserted-by":"publisher","DOI":"10.1038\/nature06932"},{"key":"e_1_3_1_6_2","doi-asserted-by":"publisher","DOI":"10.1038\/nature08940"},{"key":"e_1_3_1_7_2","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2019.00-10"},{"key":"e_1_3_1_8_2","doi-asserted-by":"publisher","DOI":"10.1002\/aelm.201800189"},{"key":"e_1_3_1_9_2","doi-asserted-by":"publisher","DOI":"10.1002\/pssr.202100208"},{"key":"e_1_3_1_10_2","doi-asserted-by":"publisher","DOI":"10.1002\/aisy.201900082"},{"key":"e_1_3_1_11_2","doi-asserted-by":"publisher","DOI":"10.1145\/3465371"},{"key":"e_1_3_1_12_2","doi-asserted-by":"publisher","DOI":"10.1109\/TETC.2023.3268137"},{"key":"e_1_3_1_13_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2019.2931188"},{"key":"e_1_3_1_14_2","volume-title":"Proceedings of the Reed-Muller Workshop","author":"Perkowski Marek","year":"2013","unstructured":"Marek Perkowski. 2013. Digital logic synthesis for memristors. In Proceedings of the Reed-Muller Workshop."},{"key":"e_1_3_1_15_2","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2017.8203782"},{"key":"e_1_3_1_16_2","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2019.8714939"},{"key":"e_1_3_1_17_2","doi-asserted-by":"publisher","DOI":"10.1145\/3400302.3415681"},{"key":"e_1_3_1_18_2","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-SOC46417.2020.9344095"},{"key":"e_1_3_1_19_2","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2021.102232"},{"key":"e_1_3_1_20_2","doi-asserted-by":"publisher","DOI":"10.1145\/3240765.3240811"},{"key":"e_1_3_1_21_2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2763171"},{"key":"e_1_3_1_22_2","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD45719.2019.8942111"},{"key":"e_1_3_1_23_2","doi-asserted-by":"publisher","DOI":"10.1109\/ASP-DAC58780.2024.10473849"},{"key":"e_1_3_1_24_2","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2016.2545412"},{"key":"e_1_3_1_25_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2014.2357292"},{"key":"e_1_3_1_26_2","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2021.3109855"},{"key":"e_1_3_1_27_2","doi-asserted-by":"publisher","DOI":"10.1002\/pssr.201800629"},{"key":"e_1_3_1_28_2","doi-asserted-by":"publisher","DOI":"10.1002\/pssr.201900033"},{"key":"e_1_3_1_29_2","doi-asserted-by":"publisher","DOI":"10.1002\/aisy.202100234"},{"key":"e_1_3_1_30_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2011.2158253"},{"key":"e_1_3_1_31_2","doi-asserted-by":"publisher","DOI":"10.7873\/DATE2014.198"},{"key":"e_1_3_1_32_2","doi-asserted-by":"publisher","DOI":"10.1002\/adma.201602418"},{"key":"e_1_3_1_33_2","doi-asserted-by":"publisher","DOI":"10.1088\/1361-6463\/aa9646"},{"key":"e_1_3_1_34_2","doi-asserted-by":"publisher","DOI":"10.1002\/adma.201802554"},{"key":"e_1_3_1_35_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2019.2926811"},{"key":"e_1_3_1_36_2","doi-asserted-by":"publisher","DOI":"10.1038\/s41598-019-51039-6"},{"key":"e_1_3_1_37_2","doi-asserted-by":"publisher","DOI":"10.1109\/JEDS.2019.2962822"},{"key":"e_1_3_1_38_2","doi-asserted-by":"publisher","DOI":"10.1002\/adfm.201704725"},{"key":"e_1_3_1_39_2","doi-asserted-by":"publisher","DOI":"10.1002\/aisy.202200207"},{"key":"e_1_3_1_40_2","doi-asserted-by":"publisher","DOI":"10.1038\/s41586-021-03748-0"},{"key":"e_1_3_1_41_2","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2016.2570248"},{"key":"e_1_3_1_42_2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2282132"},{"key":"e_1_3_1_43_2","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2016.2572726"},{"key":"e_1_3_1_44_2","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2014.7001393"},{"key":"e_1_3_1_45_2","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2015.7357108"},{"key":"e_1_3_1_46_2","doi-asserted-by":"publisher","DOI":"10.1109\/IDT.2014.7038601"},{"key":"e_1_3_1_47_2","doi-asserted-by":"publisher","unstructured":"Himanshu Bhatnagar. 2002. Advanced ASIC Chip Synthesis: Using Synopsys\u00ae Design Compiler\u2122 Physical Compiler\u2122 and Prime Time\u00ae. Springer New York NY. DOI:10.1007\/b1170-24","DOI":"10.1007\/b1170-24"},{"key":"e_1_3_1_48_2","doi-asserted-by":"publisher","DOI":"10.1145\/800125.804049"},{"key":"e_1_3_1_49_2","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2001.915010"},{"key":"e_1_3_1_50_2","doi-asserted-by":"publisher","DOI":"10.1145\/1233501.1233679"},{"key":"e_1_3_1_51_2","article-title":"The EPFL Combinational benchmark suite","author":"Amar\u00f9 Luca","year":"2015","unstructured":"Luca Amar\u00f9, Pierre-Emmanuel Gaillardon, and Giovanni De Micheli. 2015. The EPFL Combinational benchmark suite. In Proceedings of the 24th International Workshop on Logic and Synthesis. Retrieved from https:\/\/infoscience.epfl.ch\/record\/207551","journal-title":"Proceedings of the 24th International Workshop on Logic and Synthesis"}],"container-title":["ACM Transactions on Design Automation of Electronic Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3731245","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,7,9]],"date-time":"2025-07-09T12:20:45Z","timestamp":1752063645000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3731245"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,7,9]]},"references-count":50,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2025,7,31]]}},"alternative-id":["10.1145\/3731245"],"URL":"https:\/\/doi.org\/10.1145\/3731245","relation":{},"ISSN":["1084-4309","1557-7309"],"issn-type":[{"type":"print","value":"1084-4309"},{"type":"electronic","value":"1557-7309"}],"subject":[],"published":{"date-parts":[[2025,7,9]]},"assertion":[{"value":"2024-09-02","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2025-03-21","order":2,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2025-07-09","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}