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DVHetero incorporates a simulation and validation framework, SoCDiff, which enables comprehensive SoC simulation, debugging, and rapid error localization. Using this verification framework, we successfully implemented and validated the entire SoC. The SoC includes a Chisel-based CGRA generator and provides a pipelined CGRA architecture template. The CGRA is tightly integrated with the RISC-V processor, allowing for efficient DMA-based data transfer and MMIO support within the SoC. The pipelined CGRA architecture generated by DVHetero shows a 1.27\u00d7 improvement in area efficiency and a 10.54\u00d7 increase in mapping speed compared to the state-of-the-art CGRA framework, HierCGRA. Additionally, compared to state-of-the-art CGRA-SoC systems FDRA, DVHetero demonstrates a 1.67\u00d7 increase in execution speed and a 4.34\u00d7 improvement in area efficiency.<\/jats:p>","DOI":"10.1145\/3733721","type":"journal-article","created":{"date-parts":[[2025,5,2]],"date-time":"2025-05-02T12:40:15Z","timestamp":1746189615000},"page":"1-30","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["DVHetero: A Framework for Designing and Validating Heterogeneous SoC with RISC-V Processor and CGRA"],"prefix":"10.1145","volume":"18","author":[{"ORCID":"https:\/\/orcid.org\/0009-0003-5917-9914","authenticated-orcid":false,"given":"Guowei","family":"Zhu","sequence":"first","affiliation":[{"name":"School of Computer Science, Fudan University, Shanghai, China"}]},{"ORCID":"https:\/\/orcid.org\/0009-0008-7235-3098","authenticated-orcid":false,"given":"Liming","family":"Deng","sequence":"additional","affiliation":[{"name":"School of Computer Science, Fudan University, Shanghai, China"}]},{"ORCID":"https:\/\/orcid.org\/0009-0007-3150-5203","authenticated-orcid":false,"given":"Kaisen","family":"Zhang","sequence":"additional","affiliation":[{"name":"School of Microelectronics, Fudan University, Shanghai,\u00a0China"}]},{"ORCID":"https:\/\/orcid.org\/0009-0005-3340-2182","authenticated-orcid":false,"given":"Wang","family":"Fan","sequence":"additional","affiliation":[{"name":"School of Computer Science, Fudan University,\u00a0Shanghai,\u00a0China"}]},{"ORCID":"https:\/\/orcid.org\/0009-0003-2661-3876","authenticated-orcid":false,"given":"Boyin","family":"Jin","sequence":"additional","affiliation":[{"name":"School of Computer Science, Fudan University,\u00a0Shanghai,\u00a0China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0339-7093","authenticated-orcid":false,"given":"Wei","family":"Cao","sequence":"additional","affiliation":[{"name":"Institute for Big Data,\u00a0Fudan University,\u00a0Shanghai,\u00a0China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7584-1045","authenticated-orcid":false,"given":"Fengzhe","family":"Zhang","sequence":"additional","affiliation":[{"name":"Institute for Big Data, Fudan University, Shanghai,\u00a0China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4178-4094","authenticated-orcid":false,"given":"Xuegong","family":"Zhou","sequence":"additional","affiliation":[{"name":"Institute for Big Data,\u00a0Fudan University,\u00a0Shanghai,\u00a0China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7456-8377","authenticated-orcid":false,"given":"Fan","family":"Zhang","sequence":"additional","affiliation":[{"name":"Institute for Big Data,\u00a0Fudan University,\u00a0Shanghai,\u00a0China"}]},{"ORCID":"https:\/\/orcid.org\/0009-0009-4692-5803","authenticated-orcid":false,"given":"Xinsheng","family":"Yu","sequence":"additional","affiliation":[{"name":"The 32nd Research Institute of China Electronics Technology Group Corporation, Shanghai, China"}]}],"member":"320","published-online":{"date-parts":[[2025,8,18]]},"reference":[{"key":"e_1_3_1_2_2","first-page":"1","volume-title":"2023 60th ACM\/IEEE Design Automation Conference (DAC)","author":"Luk Wayne","year":"2023","unstructured":"Wayne Luk. 2023. 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