{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,7]],"date-time":"2026-02-07T20:49:01Z","timestamp":1770497341275,"version":"3.49.0"},"reference-count":55,"publisher":"Association for Computing Machinery (ACM)","issue":"4","content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2025,7,31]]},"abstract":"<jats:p>Design Space Exploration (DSE) aims at identifying Pareto optimal synthesis configurations. Previous works require microarchitecture samples with key labels, including power and clock cycles, to train their models. However, as the chip design space expands rapidly, the cost of sampling the design space has significantly increased, due to the growing number of samples and time-consuming Very Large Scale Integration (VLSI) implementation flow. Recent advancements in Large Language Models (LLMs) have demonstrated their remarkable power in zero-shot learning tasks, presenting an innovative strategy for accomplishing DSE. Hence, this article presents ChatDSE, a zero-shot framework for DSE that is powered by the advanced capabilities of the LLM GPT4.0. Firstly, this framework analyzes the nature of the target microarchitecture and generates a corresponding system context to provide the prior knowledge of the microarchitecture. Secondly, a proposed sampling algorithm, PriorDC, identifies the most representative samples with pseudo labels. One of these samples is chosen as a baseline, whose power and clock cycles labels are set as 1, and the remaining sample labels are obtained by chatting with GPT4.0. Finally, ChatDSE engages in a dialogue with GPT4.0 to estimate the power and clock cycles of designs within the space, ultimately identifying the Pareto optimal design set. In the DSE for the RISC-V Berkeley Out-of-Order Machine (BOOM), experimental results show that ChatDSE is capable of identifying optimal designs and accelerates the exploration process by 574 times when compared to the state-of-the-art DSE methodologies.<\/jats:p>","DOI":"10.1145\/3735640","type":"journal-article","created":{"date-parts":[[2025,5,16]],"date-time":"2025-05-16T07:17:24Z","timestamp":1747379844000},"page":"1-24","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["ChatDSE: A Zero-Shot Microarchitecture Design Space Explorer Powered by GPT4.0"],"prefix":"10.1145","volume":"30","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-5952-9254","authenticated-orcid":false,"given":"Mingxin","family":"Tang","sequence":"first","affiliation":[{"name":"College of Computer Science and Technology, National University of Defense Technology","place":["Changsha, China"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2876-6687","authenticated-orcid":false,"given":"Wei","family":"Chen","sequence":"additional","affiliation":[{"name":"College of Computer Science and Technology, National University of Defense Technology","place":["Changsha, China"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4439-7436","authenticated-orcid":false,"given":"Lizhou","family":"Wu","sequence":"additional","affiliation":[{"name":"College of Computer, National University of Defense Technology","place":["Changsha, China"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8307-6742","authenticated-orcid":false,"given":"Libo","family":"Huang","sequence":"additional","affiliation":[{"name":"School of Computer, National University of Defense Technology","place":["Changsha, China"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0006-1360-9650","authenticated-orcid":false,"given":"Kun","family":"Zeng","sequence":"additional","affiliation":[{"name":"School of Computer, National University of Defense Technology","place":["Changsha, China"]}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2025,7,9]]},"reference":[{"key":"e_1_3_1_2_2","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228584"},{"key":"e_1_3_1_3_2","unstructured":"A. Christopher C. Krste and P. David. 2009. The Berkeley Out-of-Order Machine (BOOM!): Computer Architecture Research Using an Industry-Competitive Synthesizable Parameterized RISC-V Processor. Technical Report. University of California Berkeley. https:\/\/www2.eecs.berkeley.edu\/Pubs\/TechRpts\/2009\/EECS-2009-113.pdf"},{"key":"e_1_3_1_4_2","volume-title":"A Highly Productive Implementation of an Out-of-Order Processor Generator","author":"Celio Christopher P.","year":"2017","unstructured":"Christopher P. Celio. 2017. A Highly Productive Implementation of an Out-of-Order Processor Generator. Ph.D. Dissertation. University of California, Berkeley."},{"key":"e_1_3_1_5_2","volume-title":"Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design","author":"Li Sicheng","year":"2022","unstructured":"Sicheng Li, Chen Bai, Xuechao Wei, Bizhao Shi, Yen-Kuang Chen, and Yuan Xie. 2022. 2022 ICCAD CAD contest problem C: Microarchitecture design space exploration. In Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design."},{"key":"e_1_3_1_6_2","volume-title":"Proceedings of the IEEE International Symposium on High Performance Computer Architecture","author":"Lee Benjamin C.","year":"2007","unstructured":"Benjamin C. Lee and David M. Brooks. 2007. Illustrative design space studies with microarchitectural regression models. In Proceedings of the IEEE International Symposium on High Performance Computer Architecture."},{"key":"e_1_3_1_7_2","volume-title":"Proceedings of the ACM SIGKDD International Conference on Knowledge Discovery and Data Mining","author":"Chen Tianqi","year":"2016","unstructured":"Tianqi Chen and Carlos Guestrin. 2016. XGBoost: A scalable tree boosting system. In Proceedings of the ACM SIGKDD International Conference on Knowledge Discovery and Data Mining."},{"key":"e_1_3_1_8_2","volume-title":"Proceedings of the IEEE International Conference on Computer Design","author":"Dou Qiang","year":"2017","unstructured":"Qiang Dou, Libo Huang, Yongweng Wen Wang, Chengyi Zhang, Tan Zhang, and Chaobing Zhou. 2017. Effective optimization of branch predictors through lightweight simulation. In Proceedings of the IEEE International Conference on Computer Design."},{"key":"e_1_3_1_9_2","doi-asserted-by":"publisher","unstructured":"Libo Huang Qi Yu Chaobing Zhou Jianqiao Ma Zhisheng Li and Qiang Dou. 2019. Efficient architectural exploration of TAGE branch predictor for embedded processors. Microelectronics Journal 88 C (2019) 88\u201398. DOI:10.1016\/j.mejo.2019.04.019","DOI":"10.1016\/j.mejo.2019.04.019"},{"key":"e_1_3_1_10_2","doi-asserted-by":"crossref","unstructured":"Chen Bai Qi Sun Jianwang Zhai Yuzhe Ma Bei Yu and Martin D. F. Wong. 2024. BOOM-Explorer: RISC-V BOOM Microarchitecture design space exploration. ACM Transactions on Design Automation of Electronic Systems 29 1 (2024) 20.","DOI":"10.1145\/3630013"},{"key":"e_1_3_1_11_2","doi-asserted-by":"crossref","unstructured":"Chen Bai Qi Sun Jianwang Zhai Yuzhe Ma Bei Yu and Martin D. F. Wong. 2021. BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration Framework. IEEE\/ACM International Conference on Computer-Aided Design (2021).","DOI":"10.1109\/ICCAD51958.2021.9643455"},{"key":"e_1_3_1_12_2","unstructured":"L. Dandan Y. Shuzhen L. Yu-Hang W. Senzhang and S. Xian-He. 2016. Efficient design space exploration via statistical sampling and adaBoost learning. In 2016 53nd ACM\/EDAC\/IEEE Design Automation Conference (DAC). ACM\/EDAC\/IEEE 839\u2013844."},{"key":"e_1_3_1_13_2","volume-title":"Proceedings of the International Symposium on High Performance Computer Architecture","author":"Lee Benjamin C.","year":"2007","unstructured":"Benjamin C. Lee and David M. Brooks. 2007. Illustrative design space studies with microarchitectural regression models. In Proceedings of the International Symposium on High Performance Computer Architecture."},{"key":"e_1_3_1_14_2","volume-title":"Proceedings of the Design Automation Conference","author":"L. Shuangnan","year":"2019","unstructured":"Shuangnan L., Francis C. M. L., and Benjamin Carrion S.2019. Accelerating FPGA prototyping through predictive model-based HLS design space exploration. In Proceedings of the Design Automation Conference."},{"key":"e_1_3_1_15_2","doi-asserted-by":"publisher","unstructured":"Engin Ipek Sally A. McKee Rich Caruana Bronis R. de Supinski and Martin Schulz. 2006. Efficiently exploring architectural design spaces via predictive modeling. SIGOPS Operating Systems Review 40 5 (December 2006) 195\u2013206. DOI:10.1145\/1168917.1168882","DOI":"10.1145\/1168917.1168882"},{"key":"e_1_3_1_16_2","volume-title":"Proceedings of the Great Lakes Symposium on VLSI","author":"Wang Duo","year":"2023","unstructured":"Duo Wang, Mingyu Yan, Yihan Teng, Dengke Han, Xiaochun Ye, and Dongrui Fan. 2023. A high-accurate multi-objective ensemble exploration framework for design space of CPU microarchitecture. In Proceedings of the Great Lakes Symposium on VLSI."},{"key":"e_1_3_1_17_2","doi-asserted-by":"crossref","unstructured":"Xin Zheng Mingjun Cheng Jiasong Chen Huaien Gao Xiaoming Xiong and Shuting Cai. 2024. BSSE: Design space exploration on the BOOM with semi-Supervised Learning. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 32 5 (May 2024) 860\u2013869.","DOI":"10.1109\/TVLSI.2024.3368075"},{"key":"e_1_3_1_18_2","doi-asserted-by":"publisher","unstructured":"Qiang Li Jun Tao and Jun Han. 2023. SPARK: An automatic Score-Power-Area efficient RISC-V processor microarchitecture SeeKer. Microelectronics Journal 132 (2023) 105679. DOI:10.1016\/j.mejo.2023.105679","DOI":"10.1016\/j.mejo.2023.105679"},{"key":"e_1_3_1_19_2","doi-asserted-by":"crossref","unstructured":"Lang Feng Wenjian Liu Chuliang Guo Ke Tang Cheng Zhuo and Zhongfeng Wang. 2023. GANDSE: Generative adversarial network-based design space exploration for neural network accelerator design. ACM Transactions on Design Automation of Electronic Systems 28 3 (2023) 1\u201320.","DOI":"10.1145\/3570926"},{"key":"e_1_3_1_20_2","doi-asserted-by":"crossref","unstructured":"Lorenzo Ferretti Andrea Cini Georgios Zacharopoulos Cesare Alippi and Laura Pozzi. 2023. Graph neural networks for high-level synthesis design space exploration. ACM Transactions on Design Automation of Electronic Systems 28 2 (2023) 1\u201320.","DOI":"10.1145\/3570925"},{"key":"e_1_3_1_21_2","doi-asserted-by":"crossref","unstructured":"Peng Liu Lizhe Wang Rajiv Ranjan Guojin He and Lei Zhao. 2022. A survey on active deep learning: From model driven to data driven. ACM Comput. Surv. 54 10 Article 221 (2022) 34 pages.","DOI":"10.1145\/3510414"},{"key":"e_1_3_1_22_2","unstructured":"Takeshi Kojima Shixiang Shane Gu and Machel Reid. 2022. Large language models are zero-shot reasoners."},{"key":"e_1_3_1_23_2","doi-asserted-by":"crossref","unstructured":"Sewon Min Mike Lewis Luke Zettlemoyer and Hannaneh Hajishirzi. 2022. MetaICL: Learning to learn in context. (2022).","DOI":"10.18653\/v1\/2022.naacl-main.201"},{"key":"e_1_3_1_24_2","unstructured":"Sang Michael Xie Aditi Raghunathan Percy Liang and Tengyu Ma. 2022. An explanation of in-context learning as implicit bayesian inference. (2022)."},{"key":"e_1_3_1_25_2","unstructured":"Qingxiu Dong Lei Li Damai Dai Ce Zheng Zhiyong Wu Baobao Chang Xu Sun Jingjing Xu Lei Li and Zhifang Sui. 2023. A survey on in-context learning. (2023)."},{"key":"e_1_3_1_26_2","unstructured":"Tom Brown Benjamin Mann Nick Ryder Melanie Subbiah Jared D. Kaplan Prafulla Dhariwal Arvind Neelakantan Pranav Shyam Girish Sastry Amanda Askell Sandhini Agarwal Ariel Herbert-Voss Gretchen Krueger Tom Henighan Rewon Child Aditya Ramesh Daniel Ziegler Jeffrey Wu Clemens Winter Chris Hesse Mark Chen Eric Sigler Mateusz Litwin Scott Gray Benjamin Chess Jack Clark Christopher Berner Sam McCandlish Alec Radford Ilya Sutskever and Dario Amodei. 2020. Language models are few-shot learners. In Advances in Neural Information Processing Systems H. Larochelle M. Ranzato R. Hadsell M. F. Balcan and H. Lin (Eds.). Vol. 33. Curran Associates Inc. 1877\u20131901. https:\/\/proceedings.neurips.cc\/paper_files\/paper\/2020\/file\/1457c0d6bfcb4967418bfb8ac142f64a-Paper.pdf"},{"key":"e_1_3_1_27_2","unstructured":"Chelsea Finn Pieter Abbeel and Sergey Levine. 2017. Model-agnostic meta-learning for fast adaptation of deep networks. In Proceedings of the 34th International Conference on Machine Learning - Volume 70 (ICML\u201917). JMLR.org 1126\u20131135."},{"key":"e_1_3_1_28_2","unstructured":"Andrei A. Rusu Dushyant Rao Jakub Sygnowski Oriol Vinyals Razvan Pascanu Simon Osindero and Raia Hadsell. 2019. Meta-Learning with latent embedding optimization. In International Conference on Learning Representations. https:\/\/openreview.net\/forum?id=BJgklhAcK7"},{"key":"e_1_3_1_29_2","doi-asserted-by":"publisher","unstructured":"Jason Blocklove Siddharth Garg Ramesh Karri and Hammond Pearce. 2023. Chip-Chat: Challenges and opportunities in conversational hardware design. In Proceedings of the 2023 ACM\/IEEE 5th Workshop on Machine Learning for CAD (MLCAD). ACM\/IEEE 1\u20136. DOI:10.1109\/MLCAD58807.2023.10299874","DOI":"10.1109\/MLCAD58807.2023.10299874"},{"key":"e_1_3_1_30_2","unstructured":"K. Chang Y. Wang H. Ren M. Wang S. Liang Y. Han H. Li and X. Li. 2023. ChipGPT: How far are we from natural language hardware design. arXiv preprint arXiv: 2305.14019 (2023)."},{"key":"e_1_3_1_31_2","unstructured":"Dong-Hyun Lee. 2013. Pseudo-Label: The simple and efficient semi-supervised learning method for deep neural networks. Retrieved July 07 2013 from https:\/\/api.semanticscholar.org\/CorpusID:18507866"},{"key":"e_1_3_1_32_2","volume-title":"Proceedings of the IEEE\/CVF Conference on Computer Vision and Pattern Recognition","author":"Pham Hieu","year":"2021","unstructured":"Hieu Pham, Zihang Dai, Qizhe Xie, and Quoc V. Le. 2021. Meta pseudo labels. In Proceedings of the IEEE\/CVF Conference on Computer Vision and Pattern Recognition."},{"key":"e_1_3_1_33_2","volume-title":"Proceedings of the International Conference on Machine Learning","author":"Yu Kai","year":"2006","unstructured":"Kai Yu, Jinbo Bi, and Volker Tresp. 2006. Active learning via transductive experimental design. In Proceedings of the International Conference on Machine Learning."},{"key":"e_1_3_1_34_2","volume-title":"Proceedings of the Design Automation Conference","author":"Liu Hung-Yi","year":"2013","unstructured":"Hung-Yi Liu and Luca P. Carloni. 2013. On learning-based methods for design-space exploration with High-Level Synthesis. In Proceedings of the Design Automation Conference."},{"key":"e_1_3_1_35_2","volume-title":"Proceedings of the International Conference on Parallel Architectures and Compilation Techniques","author":"Wei Jason","year":"2022","unstructured":"Jason Wei, Xuezhi Wang, and Dale Schuurmans. 2022. Chain of thought prompting elicits reasoning in large language models. In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques."},{"key":"e_1_3_1_36_2","unstructured":"Diederik Kingma and Jimmy Ba. 2014. Adam: A method for stochastic optimization. International Conference on Learning Representations."},{"key":"e_1_3_1_37_2","first-page":"340","volume-title":"Proceedings of the International Symposium on High Performance Computer Architecture","author":"Lee Benjamin C.","year":"2007","unstructured":"Benjamin C. Lee and David M. Brooks. 2007. Illustrative design space studies with microarchitectural regression models. In Proceedings of the International Symposium on High Performance Computer Architecture. 340\u2013351."},{"key":"e_1_3_1_38_2","doi-asserted-by":"publisher","unstructured":"Engin Ipek Sally A. McKee Karan Singh Rich Caruana Bronis R. de Supinski and Martin Schulz. 2008. Efficient architectural design space exploration via predictive modeling. ACM Transactions on Architecture and Code Optimization (TACO) 4 4 Article 1 (January 2008) 34 pages. DOI:10.1145\/1328195.1328196","DOI":"10.1145\/1328195.1328196"},{"key":"e_1_3_1_39_2","unstructured":"Christiaan Baaij Matthijs Kooijman and Jan Kuper. Cash: Structural descriptions of synchronous hardware using haskell."},{"key":"e_1_3_1_40_2","volume-title":"Proceedings of the International Conference on Field Programmable Logic and Applications","author":"Clow John","year":"2017","unstructured":"John Clow, Georgios Tzimpragos, Deeksha Dangwal, Sammy Guo, Joseph McMahan, and Timothy Sherwood. 2017. A pythonic approach for rapid hardware prototyping and instrumentation. In Proceedings of the International Conference on Field Programmable Logic and Applications."},{"key":"e_1_3_1_41_2","doi-asserted-by":"publisher","unstructured":"Niket K. Choudhary Salil V. Wadhavkar Tanmay A. Shah Hiran Mayukh Jayneel Gandhi Brandon H. Dwiel Sandeep Navada Hashem H. Najaf-abadi and Eric Rotenberg. 2011. FabScalar: Composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template. ACM SIGARCH Computer Architecture News 39 3 (June 2011) 11\u201322. DOI:10.1145\/2024723.2000067","DOI":"10.1145\/2024723.2000067"},{"key":"e_1_3_1_42_2","doi-asserted-by":"publisher","unstructured":"Tejas S. Karkhanis and James E. Smith. 2007. Automated design of application-specific superscalar processors: An analytical approach. ACM SIGARCH Computer Architecture News 35 2 (May 2007) 402\u2013411. DOI:10.1145\/1273440.1250712","DOI":"10.1145\/1273440.1250712"},{"key":"e_1_3_1_43_2","volume-title":"Proceedings of the International Conference on Parallel Architectures and Compilation Techniques","author":"Navada Sandeep","year":"2010","unstructured":"Sandeep Navada, Niket K. Choudhary, and Eric Rotenberg. 2010. Criticality-driven superscalar design space exploration. In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques."},{"key":"e_1_3_1_44_2","volume-title":"Proceedings of the IEEE\/ACM International Symposium on Microarchitecture","author":"Bai C.","year":"2023","unstructured":"C. Bai, J. Huang, X. Wei, Y. Ma, S. Li, H. Zheng, B. Yu, and Y. Xie. 2023. ArchExplorer: Microarchitecture exploration via bottleneck analysis. In Proceedings of the IEEE\/ACM International Symposium on Microarchitecture."},{"key":"e_1_3_1_45_2","volume-title":"Proceedings of the International Symposium on VLSI Design, Automation and Test","author":"Schafer Benjamin Carrion","year":"2009","unstructured":"Benjamin Carrion Schafer, Takashi Takenaka, and Kazutoshi Wakabayashi. 2009. Adaptive simulated annealer for high level synthesis design space exploration. In Proceedings of the International Symposium on VLSI Design, Automation and Test."},{"key":"e_1_3_1_46_2","first-page":"65","article-title":"Parallel high-level synthesis design space exploration for behavioral ips of exact latencies(Article)","author":"Schafer B. C. Email Author View Correspondence (jump link)","year":"2017","unstructured":"B. C. Email Author View Correspondence (jump link) Schafer. 2017. Parallel high-level synthesis design space exploration for behavioral ips of exact latencies(Article). ACM Transactions on Design Automation of Electronic Systems 4 (2017), 65.","journal-title":"ACM Transactions on Design Automation of Electronic Systems"},{"key":"e_1_3_1_47_2","volume-title":"Proceedings of the International Symposium on Electronic System Design","author":"Mishra Vipul Kumar","year":"2014","unstructured":"Vipul Kumar Mishra and Anirban Sengupta. 2014. PSDSE: Particle swarm driven design space exploration of architecture and unrolling factors for nested loops in high level synthesis. In Proceedings of the International Symposium on Electronic System Design."},{"key":"e_1_3_1_48_2","volume-title":"Proceedings of the International Conference on Knowledge-based and Intelligent Information and Engineering Systems","author":"Sengupta Anirban","year":"2014","unstructured":"Anirban Sengupta and Saumya Bhadauria. 2014. Exploration of multi-objective tradeoff during high level synthesis using bacterial chemotaxis and dispersal. In Proceedings of the International Conference on Knowledge-based and Intelligent Information and Engineering Systems."},{"key":"e_1_3_1_49_2","volume-title":"Proceedings of the IEEE Symposium on Security and Privacy","author":"Pearce H.","year":"2022","unstructured":"H. Pearce, B. Ahmad, B. Tan, B. Dolan-gavitt, and R. Karri. 2022. Asleep at the keyboard? Assessing the security of GitHub Copilot\u2019s code contributions. In Proceedings of the IEEE Symposium on Security and Privacy."},{"key":"e_1_3_1_50_2","volume-title":"Proceedings of the IEEE Symposium on Security and Privacy","author":"Pearce Hammond","year":"2023","unstructured":"Hammond Pearce, Benjamin Tan, Baleegh Ahmad, Ramesh Karri, and Brendan Dolan-Gavitt. 2023. Examining zero-shot vulnerability repair with large language models. In Proceedings of the IEEE Symposium on Security and Privacy."},{"key":"e_1_3_1_51_2","doi-asserted-by":"publisher","unstructured":"Haoyuan Wu Zhuolun He Xinyun Zhang Xufeng Yao Su Zheng Haisheng Zheng and Bei Yu. 2024. ChatEDA: A large language model powered autonomous agent for EDA. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 43 10 (2024) 3184\u20133197. DOI:10.1109\/TCAD.2024.3383347","DOI":"10.1109\/TCAD.2024.3383347"},{"key":"e_1_3_1_52_2","unstructured":"Robert Kirby Chris Cheng Nathaniel Pinckney Rongjian Liang Jonah Alben Himyanshu Anand Sanmitra Banerjee Ismet Bayraktaroglu Bonita Bhaskaran Bryan Catanzaro Arjun Chaudhuri Sharon Clay Bill Dally Laura Dang Parikshit Deshpande Siddhanth Dhodhi Sameer Halepete Eric Hill Jiashang Hu Sumit Jain Ankit Jindal Brucek Khailany George Kokai Kishor Kunal Xiaowei Li Charley Lind Hao Liu Stuart Oberman Sujeet Omar Ghasem Pasandi Sreedhar Pratty Jonathan Raiman Ambar Sarkar Zhengjiang Shao Hanfei Sun Pratik P Suthar Varun Tej Walker Turner Kaizhe Xu Haoxing Ren Mingjie Liu Teodor-Dumitru Ene. 2023. Chipnemo: Domainadapted llms for chip design. arXiv preprint arXiv: 2311.00176 (2023)."},{"key":"e_1_3_1_53_2","volume-title":"Proceedings of the ACM\/IEEE 2nd Workshop on Machine Learning for CAD","author":"Pearce Hammond","year":"2020","unstructured":"Hammond Pearce, Benjamin Tan, and Ramesh Karri. 2020. DAVE: Deriving automatically verilog from English. In Proceedings of the ACM\/IEEE 2nd Workshop on Machine Learning for CAD."},{"key":"e_1_3_1_54_2","volume-title":"Proceedings of the Design, Automation and Test in Europe Conference and Exhibition","author":"Thakur S.","year":"2023","unstructured":"S. Thakur, B. Ahmad, Z. Fan, H. Pearce, B. Tan, R. Karri, B. Dolan-Gavitt, and S. Garg. 2023. Benchmarking large language models for automated verilog RTL code generation. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition."},{"key":"e_1_3_1_55_2","doi-asserted-by":"publisher","unstructured":"Chenwei Xiong Cheng Liu Huawei Li and Xiaowei Li. 2024. HLSPilot: LLM-based high-level synthesis. In Proceedings of the 43rd IEEE\/ACM International Conference on Computer-Aided Design (ICCAD\u201924). ACM New York NY USA Article 226 9 pages. DOI:10.1145\/3676536.3676781","DOI":"10.1145\/3676536.3676781"},{"key":"e_1_3_1_56_2","doi-asserted-by":"publisher","unstructured":"Yuxuan Yin YuWang Boxun Xu and Peng Li. 2024. ADO-LLM: Analog Design Bayesian Optimization with In-Context Learning of Large Language Models. In Proceedings of the 43rd IEEE\/ACM International Conference on Computer-Aided Design (ICCAD\u201924). ACM\/IEEE New York NY USA Article 81 9 pages. DOI:10.1145\/3676536.3676816","DOI":"10.1145\/3676536.3676816"}],"container-title":["ACM Transactions on Design Automation of Electronic Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3735640","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,7,9]],"date-time":"2025-07-09T12:21:01Z","timestamp":1752063661000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3735640"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,7,9]]},"references-count":55,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2025,7,31]]}},"alternative-id":["10.1145\/3735640"],"URL":"https:\/\/doi.org\/10.1145\/3735640","relation":{},"ISSN":["1084-4309","1557-7309"],"issn-type":[{"value":"1084-4309","type":"print"},{"value":"1557-7309","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,7,9]]},"assertion":[{"value":"2024-10-17","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2025-04-28","order":2,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2025-07-09","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}