{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,21]],"date-time":"2025-11-21T11:32:51Z","timestamp":1763724771390,"version":"3.41.2"},"reference-count":30,"publisher":"Association for Computing Machinery (ACM)","issue":"4","funder":[{"name":"Intel Center for Heterogeneous Integrated Platforms"},{"name":"Swiss NSF Edge-Companions","award":["10002812"],"award-info":[{"award-number":["10002812"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2025,7,31]]},"abstract":"<jats:p>Full-System (FS) simulation is essential for performance evaluation of complete systems that execute complex applications on a complete software stack consisting of an operating system and user applications. Nevertheless, they require careful fine-tuning against real hardware to obtain reliable performance statistics, which can become tedious, error-prone, and time-consuming with typical trial-and-error approaches. We propose a novel, streamlined, component-level calibration methodology to address these shortcomings to validate FS simulation models. Our methodology greatly accelerates the validation process without sacrificing accuracy. It is Instruction Set Architecture (ISA)-agnostic, and can tackle hardware specifications at different levels of detail. We demonstrate its effectiveness by validating FS models against both open-hardware and IP-protected (closed hardware) RISC-V silicon, achieving a mean error of 19%\u201323% for the SPEC CPU2017 suite in the two cases. We introduce the first open-source RISC-V-based FS-validated simulation models with a complete and replicable methodology.<\/jats:p>","DOI":"10.1145\/3737876","type":"journal-article","created":{"date-parts":[[2025,6,4]],"date-time":"2025-06-04T07:31:52Z","timestamp":1749022312000},"page":"1-19","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["Towards Accurate RISC-V Full System Simulation via Component-Level Calibration"],"prefix":"10.1145","volume":"24","author":[{"ORCID":"https:\/\/orcid.org\/0009-0001-6140-3095","authenticated-orcid":false,"given":"Karan","family":"Pathak","sequence":"first","affiliation":[{"name":"Electrical Engineering, Ecole Polytechnique Federale de Lausanne","place":["Lausanne, Switzerland"]},{"name":"Faculty of Electrical Engineering, Mathematics and Computer Science, Delft University of Technology","place":["Lausanne, Switzerland"]},{"name":"Haute ecole d'ingenierie et de gestion du canton de Vaud Institut Reconfigurable & Embedded Digital Systems","place":["Lausanne, Switzerland"]}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4958-9990","authenticated-orcid":false,"given":"Joshua","family":"Klein","sequence":"additional","affiliation":[{"name":"Electrical Engineering, Ecole Polytechnique Federale de Lausanne","place":["Lausanne, Switzerland"]}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8940-3775","authenticated-orcid":false,"given":"Giovanni","family":"Ansaloni","sequence":"additional","affiliation":[{"name":"Electrical Engineering, Ecole Polytechnique Federale de Lausanne","place":["Lausanne, Switzerland"]}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8961-0387","authenticated-orcid":false,"given":"Said","family":"Hamdioui","sequence":"additional","affiliation":[{"name":"Faculty of Electrical Engineering, Mathematics and Computer Science, Delft University of Technology","place":["Delft, Netherlands"]}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3678-7007","authenticated-orcid":false,"given":"Georgi","family":"Gaydadjiev","sequence":"additional","affiliation":[{"name":"Faculty of Electrical Engineering, Mathematics and Computer Science, Delft University of Technology","place":["Delft, Netherlands"]},{"name":"Computer Science and Engineering, Chalmers University of Technology","place":["Delft, Netherlands"]}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6971-1965","authenticated-orcid":false,"given":"Marina","family":"Zapater","sequence":"additional","affiliation":[{"name":"Reconfigurable and Embedded Digital Systems, Haute ecole d'ingenierie et de gestion du canton de Vaud","place":["Yverdon-les-Bains, Switzerland"]},{"name":"Electrical Engineering, Ecole polytechnique federale de Lausanne","place":["Yverdon-les-Bains, Switzerland"]}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9536-4947","authenticated-orcid":false,"given":"David","family":"Atienza","sequence":"additional","affiliation":[{"name":"Electrical Engineering, Ecole Polytechnique Federale de Lausanne","place":["Lausanne, Switzerland"]}]}],"member":"320","published-online":{"date-parts":[[2025,7,11]]},"reference":[{"key":"e_1_3_2_2_2","doi-asserted-by":"publisher","DOI":"10.1109\/PMBS49563.2019.00012"},{"key":"e_1_3_2_3_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCC-CSS-ICESS.2015.166"},{"key":"e_1_3_2_4_2","unstructured":"Fabrice Bellard. 2005. QEMU a fast and portable dynamic translator. In Proceedings of the Annual Conference on USENIX Annual Technical Conference (ATEC\u201905) USENIX Association Anaheim CA 41."},{"key":"e_1_3_2_5_2","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"e_1_3_2_6_2","doi-asserted-by":"publisher","DOI":"10.1109\/MCSoC.2016.20"},{"key":"e_1_3_2_7_2","doi-asserted-by":"publisher","DOI":"10.1109\/ReCoSoC.2012.6322869"},{"key":"e_1_3_2_8_2","first-page":"1","volume-title":"Proceedings of the Workshop on RISC-V for Computer Architecture Research","author":"Chatzopoulos Odysseas","year":"2021","unstructured":"Odysseas Chatzopoulos, George-Marios Fragkoulis, George Papadimitriou, and Dimitris Gizopoulos. 2021. Towards accurate performance modeling of RISC-V designs. In Proceedings of the Workshop on RISC-V for Computer Architecture Research. 1\u20138."},{"key":"e_1_3_2_9_2","doi-asserted-by":"publisher","DOI":"10.3389\/fbioe.2020.00496"},{"key":"e_1_3_2_10_2","doi-asserted-by":"publisher","DOI":"10.1145\/379240.565338"},{"key":"e_1_3_2_11_2","doi-asserted-by":"publisher","DOI":"10.1109\/SAMOS.2014.6893220"},{"key":"e_1_3_2_12_2","doi-asserted-by":"crossref","unstructured":"Alexander D\u00f6rflinger Mark Albers Benedikt Kleinbeck Yejun Guan Harald Michalik Raphael Klink Christopher Blochwitz Anouar Nechi and Mladen Berekovic. 2021. A comparative survey of open-source application-class RISC-V processor implementations. In Proceedings of the 18th ACM International Conference on Computing Frontiers.","DOI":"10.1145\/3457388.3458657"},{"volume-title":"gXR5: A gem5-based Full-system RISC-V Simulator","year":"2020","key":"e_1_3_2_13_2","unstructured":"Joshu Klein, Yasir Qureshi, Marina Zapater, and David Atienza. 2020. gXR5: A gem5-based Full-system RISC-V Simulator. Retrieved January 10, 2023 from https:\/\/www.epfl.ch\/labs\/esl\/research\/2d-3d-system-on-chip\/gXR5"},{"volume-title":"The Rocket Chip Generator","year":"2021","key":"e_1_3_2_14_2","unstructured":"Krste Asanovi\u0107, Rimas Avizienis, Jonathan Bachrach, Scott Beamer, David Biancolin, Christopher Celio, Henry Cook, Daniel Dabbelt, John Hauser, Adam Izraelevitz, Sagar Karandikar, Ben Keller, Donggyu Kim, John Koenig, Yunsup Lee, Eric Love, Martin Maas, Albert Magyar, Howard Mao, Miquel Moreto, Albert Ou, David A. Patterson, Brian Richards, Colin Schmidt Stephen Twigg, Huy Vo, and Andrew Waterman. 2021. The Rocket Chip Generator. Retrieved March 01, 2023 from http:\/\/www2.eecs.berkeley.edu\/Pubs\/TechRpts\/2016\/EECS-2016-17.html"},{"key":"e_1_3_2_15_2","doi-asserted-by":"publisher","unstructured":"Baptiste Gregorutti Bertrand Michel and Philippe Saint-Pierre. 2017. Correlation and variable importance in random forests. Statistics and Computing 27 (2017). DOI:10.1007\/s11222-016-9646-1","DOI":"10.1007\/s11222-016-9646-1"},{"key":"e_1_3_2_16_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2014.6844457"},{"key":"e_1_3_2_17_2","first-page":"14","volume-title":"Proceedings of the 5th Workshop on Computer Architecture Research with RISC-V","author":"Hin Peter Yuen Ho","year":"2021","unstructured":"Peter Yuen Ho Hin, Xiongfei Liao, Jin Cui, Andrea Mondelli, Thannirmalai Muthukaruppan Somu, and Naxin Zhang. 2021. Supporting RISC-V full system simulation in gem5. In Proceedings of the 5th Workshop on Computer Architecture Research with RISC-V. 14\u201319."},{"key":"e_1_3_2_18_2","doi-asserted-by":"publisher","DOI":"10.23919\/DATE51398.2021.9474108"},{"key":"e_1_3_2_19_2","doi-asserted-by":"publisher","DOI":"10.1016\/j.bbe.2022.11.005"},{"key":"e_1_3_2_20_2","doi-asserted-by":"publisher","DOI":"10.23919\/DATE56975.2023.10137080"},{"key":"e_1_3_2_21_2","volume-title":"Combining Branch Predictors","author":"McFarling S.","year":"1993","unstructured":"S. McFarling. 1993. Combining Branch Predictors. Technical Report. 250 University Avenue Palo Alto, California 94301 USA."},{"key":"e_1_3_2_22_2","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-SoC57769.2023.10321912"},{"key":"e_1_3_2_23_2","first-page":"2","volume-title":"Proceedings of the RISC-V Summit Europe, Barcelona","author":"Pathak Karan","year":"2023","unstructured":"Karan Pathak, Johsua Klein, Giovanni Ansaloni, Marina Zapater, and David Atienza. 2023. Validating full-system RISC-V simulator: A systematic approach. In Proceedings of the RISC-V Summit Europe, Barcelona (Barcelona, Spain). RISC-V Summit Europe, Barcelona, Spain, 2 pages."},{"key":"e_1_3_2_24_2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2023.3347675"},{"key":"e_1_3_2_25_2","doi-asserted-by":"publisher","DOI":"10.23919\/SpringSim.2019.8732862"},{"key":"e_1_3_2_26_2","volume-title":"Simulation of RISC-V based Systems in gem5","author":"Scheffel Robert","year":"2018","unstructured":"Robert Scheffel. 2018. Simulation of RISC-V based Systems in gem5. Master\u2019s Thesis. TU Dresden."},{"key":"e_1_3_2_27_2","volume-title":"Stress-ng","author":"wiki ubuntu","year":"2020","unstructured":"ubuntu wiki. 2020. Stress-ng. Retrieved January 01, 2023 from https:\/\/wiki.ubuntu.com\/Kernel\/Reference\/stress-ng"},{"key":"e_1_3_2_28_2","unstructured":"SiFive FU540-C000 Manual v1p4. 2021. Retrieved January 01 2023 from https:\/\/sifive.cdn.prismic.io\/sifive\/d3ed5cd0-6e74-46b2-a12d-72b06706513e_fu540-c000-manual-v1p4.pdf"},{"key":"e_1_3_2_29_2","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2022.104599"},{"key":"e_1_3_2_30_2","doi-asserted-by":"publisher","DOI":"10.3390\/app12178654"},{"key":"e_1_3_2_31_2","doi-asserted-by":"publisher","DOI":"10.23919\/DATE56975.2023.10137178"}],"container-title":["ACM Transactions on Embedded Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3737876","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,7,16]],"date-time":"2025-07-16T11:58:38Z","timestamp":1752667118000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3737876"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,7,11]]},"references-count":30,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2025,7,31]]}},"alternative-id":["10.1145\/3737876"],"URL":"https:\/\/doi.org\/10.1145\/3737876","relation":{},"ISSN":["1539-9087","1558-3465"],"issn-type":[{"type":"print","value":"1539-9087"},{"type":"electronic","value":"1558-3465"}],"subject":[],"published":{"date-parts":[[2025,7,11]]},"assertion":[{"value":"2024-08-05","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2025-05-09","order":2,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2025-07-11","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}